SLUS987C January   2011  – December 2019 BQ33100

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General Purpose I/O
    6. 7.6  Supply Current
    7. 7.7  REG27 LDO
    8. 7.8  Coulomb Counter
    9. 7.9  ADC
    10. 7.10 External Capacitor Voltage Balance Drive
    11. 7.11 Capacitor Voltage Monitor
    12. 7.12 Internal Temperature Sensor
    13. 7.13 Thermistor Measurement Support
    14. 7.14 Internal Thermal Shutdown
    15. 7.15 High-Frequency Oscillator
    16. 7.16 Low-Frequency Oscillator
    17. 7.17 RAM Backup
    18. 7.18 Flash
    19. 7.19 Current Protection Thresholds
    20. 7.20 Current Protection Timing
    21. 7.21 Timing Requirements: SMBus
    22. 7.22 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Super Capacitor Measurements
        1. 8.1.1.1 Voltage
        2. 8.1.1.2 Current, Charge, and Discharge Counting
        3. 8.1.1.3 Device Calibration
        4. 8.1.1.4 Temperature
        5. 8.1.1.5 Series Capacitor Configuration
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Capacitance Monitoring and Learning
        1. 8.3.1.1 Monitoring and Control Operational Overview
        2. 8.3.1.2 Main Monitoring Registers
        3. 8.3.1.3 Initial Capacitance at Device Reset
        4. 8.3.1.4 Qualified Capacitance Learning
        5. 8.3.1.5 Health Determination
        6. 8.3.1.6 ESR Measurement
        7. 8.3.1.7 Monitor Operating Modes
      2. 8.3.2 Capacitor Voltage Balancing
      3. 8.3.3 Charge Control
        1. 8.3.3.1 Charge Termination
        2. 8.3.3.2 CHG Override Control
      4. 8.3.4 Lifetime Data Gathering
        1. 8.3.4.1 Lifetime Maximum Temperature
        2. 8.3.4.2 Lifetime Minimum Temperature
        3. 8.3.4.3 Lifetime Maximum Capacitor Voltage
      5. 8.3.5 Safety Detection Features
        1. 8.3.5.1  Capacitor Overvoltage (OV)
        2. 8.3.5.2  Capacitor Voltage Imbalance (CIM)
        3. 8.3.5.3  Weak Capacitor (CLBAD)
        4. 8.3.5.4  Overtemperature (OT)
        5. 8.3.5.5  Overcurrent During Charging (OC Chg)
        6. 8.3.5.6  Overcurrent During Discharging (OC Dsg)
        7. 8.3.5.7  Short-Circuit During Charging (SC Chg)
        8. 8.3.5.8  Short-Circuit During Discharging (SC Dsg)
        9. 8.3.5.9  AFE Watchdog (WDF)
        10. 8.3.5.10 Integrated AFE Communication Fault (AFE_C)
        11. 8.3.5.11 Data Flash Fault (DFF)
        12. 8.3.5.12 FAULT Indication (FAULT Pin)
      6. 8.3.6 Communications
        1. 8.3.6.1 SMBus On and Off State
      7. 8.3.7 Security (Enables and Disables Features)
      8. 8.3.8 Measurement System Calibration
        1. 8.3.8.1  Coulomb Counter Deadband
        2. 8.3.8.2  Auto Calibration
        3. 8.3.8.3  Current Gain
        4. 8.3.8.4  CC Delta
        5. 8.3.8.5  Cap1 K-factor
        6. 8.3.8.6  Cap2 K-factor
        7. 8.3.8.7  Cap3 K-factor
        8. 8.3.8.8  Cap4 K-factor
        9. 8.3.8.9  Cap5 K-factor
        10. 8.3.8.10 K-factor Override Flag
        11. 8.3.8.11 System Voltage K-factor
        12. 8.3.8.12 Stack Voltage K-factor
        13. 8.3.8.13 K-factor Stack Override Flag
        14. 8.3.8.14 CC Offset
        15. 8.3.8.15 Board Offset
        16. 8.3.8.16 Int Temp Offset
        17. 8.3.8.17 Ext1 Temp Offset
        18. 8.3.8.18 CC Current
        19. 8.3.8.19 Voltage Signal
        20. 8.3.8.20 Temp Signal
        21. 8.3.8.21 CC Offset Time
        22. 8.3.8.22 ADC Offset Time
        23. 8.3.8.23 Current Gain Time
        24. 8.3.8.24 Voltage Time
        25. 8.3.8.25 Temperature Time
        26. 8.3.8.26 Cal Mode Timeout
        27. 8.3.8.27 Ext Coef a1..a5, b1..b4, Ext rc0, Ext adc0
        28. 8.3.8.28 Rpad
        29. 8.3.8.29 Rint
        30. 8.3.8.30 Int Coef 1..4, Int Min AD, Int Max Temp
        31. 8.3.8.31 Filter
        32. 8.3.8.32 Deadband
        33. 8.3.8.33 CC Deadband
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Power Modes
    5. 8.5 Programming
      1. 8.5.1 Communications
        1. 8.5.1.1 BQ33100 Slave Address
        2. 8.5.1.2 SMBus On and Off State
        3. 8.5.1.3 Packet Error Checking
      2. 8.5.2 SBS Commands
        1. 8.5.2.1 SBS Command Summary
        2. 8.5.2.2 SBS Command Details
          1. 8.5.2.2.1  ManufacturerAccess (0x00)
            1. 8.5.2.2.1.1  Device Type (0x0001)
            2. 8.5.2.2.1.2  Firmware Version (0x0002)
            3. 8.5.2.2.1.3  Hardware Version (0x0003)
            4. 8.5.2.2.1.4  DF Checksum (0x0004)
            5. 8.5.2.2.1.5  Seal Device (0x0020)
            6. 8.5.2.2.1.6  Lifetime and Capacitor Balancing Enable (0x0021)
            7. 8.5.2.2.1.7  FAULT Activation (0x0030)
            8. 8.5.2.2.1.8  FAULT Clear (0x0031)
            9. 8.5.2.2.1.9  CHGLVL0 Activation (0x0032)
            10. 8.5.2.2.1.10 CHGLVL0 Clear (0x0033)
            11. 8.5.2.2.1.11 CHGLVL1 Activation (0x0033)
            12. 8.5.2.2.1.12 CHGLVL1 Clear (0x0034)
            13. 8.5.2.2.1.13 Learn Load Activation (0x0037)
            14. 8.5.2.2.1.14 Learn Load Clear (0x0038)
            15. 8.5.2.2.1.15 Calibration Mode (0x0040)
            16. 8.5.2.2.1.16 Reset (0x0041)
            17. 8.5.2.2.1.17 Unseal Device (UnsealKey)
            18. 8.5.2.2.1.18 Extended SBS Commands
          2. 8.5.2.2.2  Temperature (0x08)
          3. 8.5.2.2.3  Voltage (0x09)
          4. 8.5.2.2.4  Current (0x0A)
          5. 8.5.2.2.5  ESR (0x0B)
          6. 8.5.2.2.6  RelativeStateofCharge (0x0D)
          7. 8.5.2.2.7  Health (0x0E)
          8. 8.5.2.2.8  Capacitance (0x10)
          9. 8.5.2.2.9  ChargingCurrent (0x14)
          10. 8.5.2.2.10 ChargingVoltage (0x15)
          11. 8.5.2.2.11 CapacitorVoltage5..1 (0x3B..0x3F)
          12. 8.5.2.2.12 Extended SBS Commands
            1. 8.5.2.2.12.1 FETControl(0x46)
            2. 8.5.2.2.12.2 SafetyAlert (0x50)
            3. 8.5.2.2.12.3 SafetyStatus (0x51)
            4. 8.5.2.2.12.4 OperationStatus (0x54)
            5. 8.5.2.2.12.5 SystemVoltage (0x5a)
            6. 8.5.2.2.12.6 UnSealKey(0x60)
            7. 8.5.2.2.12.7 ManufacturerInfo(0x70)
      3. 8.5.3 Data Flash
        1. 8.5.3.1 Accessing Data Flash
        2. 8.5.3.2 Data Flash Interface
        3. 8.5.3.3 Data Flash Summary
        4. 8.5.3.4 Specific Data Flash Programming Details
          1. 8.5.3.4.1  OC Dsg
          2. 8.5.3.4.2  OC Dsg Time
          3. 8.5.3.4.3  SC Dsg Cfg
          4. 8.5.3.4.4  SC Chg Cfg
          5. 8.5.3.4.5  Initial 1st Capacitance
          6. 8.5.3.4.6  Capacitance
          7. 8.5.3.4.7  Firmware Version
          8. 8.5.3.4.8  Hardware Version
          9. 8.5.3.4.9  Manuf. Info
          10. 8.5.3.4.10 Operation Cfg
          11. 8.5.3.4.11 FET ACTION
          12. 8.5.3.4.12 FAULT
          13. 8.5.3.4.13 AFE State_CTL
          14. 8.5.3.4.14 Measurement Margin %
          15. 8.5.3.4.15 Max Dsg Time
          16. 8.5.3.4.16 V Chg Nominal
          17. 8.5.3.4.17 V Chg A
          18. 8.5.3.4.18 V Chg B
          19. 8.5.3.4.19 V Chg Max
          20. 8.5.3.4.20 Min Voltage
          21. 8.5.3.4.21 Learning Frequency
          22. 8.5.3.4.22 Dsg Current Threshold
          23. 8.5.3.4.23 Chg Current Threshold
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting Number of Series Capacitor Support
        2. 9.2.2.2 Selecting Charging Voltage Values
        3. 9.2.2.3 Learning Frequency Selection
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

PW Package
24-Pin TSSOP
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
CHG 23 O P-Channel FET drive for controlling charge
CHGLVL0 11 O Charge Control Output 0
CHGLVL1 12 O Charge Control Output 1
CHGOR 21 I CHG override input. If not used, connect to VSS.
FAULT 15 O Active high output to indicate fault condition
GND 19 P Ground
LLEN 17 O Learn Load Enable Output
NC 2 O Not used and must be connected to VCC
NC 22 — No connect. Leave the NC pin floating.
RBI 18 P RAM backup pin to provide backup potential to the internal DATA RAM if power is momentarily lost by using a capacitor attached between RBI and GND.
REG27 20 P Internal power supply 2.7-V bias output
SCL 16 I/OD Serial clock input: Clocks data on SDA
SDA 14 I/OD Serial data: transmits and receives data
SRN 8 IA Analog input pin connected to the internal ADC peripheral for measuring a small voltage between SRP and SRN where SRN is the bottom of the sense resistor.
SRP 7 IA Analog input pin connected to the internal ADC peripheral for measuring a small voltage between SRP and SRN where SRP is the top of the sense resistor.
TS 9 IA Thermistor input
VC1 3 IA Sense voltage input terminal and external capacitor voltage balancing drive output for the 5th-series capacitor, and stack measurement input. See Series Capacitor Configuration for systems with less than 5 series.
VC2 4 IA Sense voltage input terminal and external capacitor voltage balancing drive output for the 4th-series capacitor. See Series Capacitor Configuration for systems with less than 5 series.
VC3 5 IA Sense voltage input terminal and external capacitor voltage balancing drive output for the 3rd-series capacitor. See Series Capacitor Configuration for systems with less than 5 series.
VC4 6 IA Sense voltage input terminal and external capacitor voltage balancing drive output for the 2nd-series capacitor. See Series Capacitor Configuration for systems with less than 5 series.
VC5 10 IA Sense voltage input terminal and external capacitor voltage balancing drive output for the 1st capacitor. See Series Capacitor Configuration for systems with less than 5 series.
VC5BAL 13 O Cell balance control output for the least positive capacitor (only used in a 5-series capacitor configuration)
VCCPACK 1 P Power supply from the super capacitors. The top of the super capacitor stack must be connected to this pin.
VCC 24 P Positive input from power supply
(1) I = Input, O = Output, P = Power, IA = Analog Input, OD = Open Drain