SLUSAQ3H November   2011  – June 2024 UCC27523 , UCC27525 , UCC27526

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Undervoltage Lockout
      2. 7.3.2 Operating Supply Current
      3. 7.3.3 Input Stage
      4. 7.3.4 Enable Function
      5. 7.3.5 Output Stage
      6. 7.3.6 Low Propagation Delays and Tightly Matched Outputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input-to-Output Logic
        2. 8.2.2.2 Enable and Disable Function
        3. 8.2.2.3 VDD Bias Supply Voltage
        4. 8.2.2.4 Propagation Delay
        5. 8.2.2.5 Drive Current and Power Dissipation
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

UCC27523 UCC27525 UCC27526 D, DGN, Package UCC2752(3,5)8-Pin SOIC-8, HVSSOPTop View Figure 5-1 D, DGN, Package UCC2752(3,5)8-Pin SOIC-8, HVSSOPTop View
UCC27523 UCC27525 UCC27526 DSD Package UCC2752(3,5)8-Pin WSONTop View Figure 5-2 DSD Package UCC2752(3,5)8-Pin WSONTop View
UCC27523 UCC27525 UCC27526 DSD Package UCC275268-Pin WSONTop View Figure 5-3 DSD Package UCC275268-Pin WSONTop View
Table 5-1 Pin Functions (UCC27523 / UCC27525)
PIN I/O DESCRIPTION
NO. NAME
1 ENA I Enable input for Channel A: ENA biased LOW Disables Channel A output regardless of INA state, ENA biased HIGH or floating Enables Channel A output, ENA allowed to float hence the pin-to-pin compatibility with UCC2732X N/C pin.
2 INA I Input to Channel A: Inverting Input in UCC27523, Non-Inverting Input in UCC27524, Inverting Input in UCC27525, OUTA held LOW if INA is unbiased or floating.
3 GND - Ground: All signals referenced to this pin.
4 INB I Input to Channel B: Inverting Input in UCC27523, Non-Inverting Input in UCC27524, Non-Inverting Input in UCC27525, OUTB held LOW if INB is unbiased or floating.
5 OUTB O Output of Channel B
6 VDD I Bias supply input
7 OUTA O Output of Channel A
8 ENB I Enable input for Channel B: ENB biased LOW Disables Channel B output regardless of INB state, ENB biased HIGH or floating Enables Channel B output, ENB allowed to float hence the pin-to-pin compatibility with UCC2732X N/C pin.
Table 5-2 Pin Functions (UCC27526)
PIN I/O DESCRIPTION
NO. NAME
1 INA– I Inverting Input to Channel A: When Channel A is used in Non-Inverting configuration, connect INA– to GND in order to Enable Channel A output, OUTA held LOW if INA– is unbiased or floating.
2 INB– I Inverting Input to Channel B: When Channel B is used in Non-Inverting configuration, connect INB– to GND in order to Enable Channel B output, OUTB held LOW if INB– is unbiased or floating.
3 GND - Ground: All signals referenced to this pin.
4 OUTB I Output of Channel B
5 VDD O Bias Supply Input
6 OUTA I Output of Channel A
7 INB+ O Non-Inverting Input to Channel B: When Channel B is used in Inverting configuration, connect INB+ to VDD in order to Enable Channel B output, OUTB held LOW if INB+ is unbiased or floating.
8 INA+ I Non-Inverting Input to Channel A: When Channel A is used in Inverting configuration, connect INA+ to VDD in order to Enable Channel A output, OUTA held LOW if INA+ is unbiased or floating.