9.4.1.1 Input Overvoltage Protection

The IC provides a built-in input overvoltage protection to protect the device and other components against damage if the input voltage (Voltage from VBUS to PGND) goes too high. When an input overvoltage condition is detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT pin. Once V_BUS drops below the input overvoltage exit threshold, the fault is cleared and charge process resumes.

9.4.1.2 Bad Adaptor Detection/Rejection

Although not shown in Figure 14, at power-on-reset (POR) of VBUS, the IC performs the bad adaptor detection by applying a current sink to VBUS. If the VBUS is higher than V_IN(MIN) for 30ms, the adaptor is good and the charge process begins. Otherwise, if the VBUS drops below V_IN(MIN), a bad adaptor is detected. Then, the IC disables the current sink, sends a send fault pulse in FAULT pin and sets the bad adaptor flag (B2 - B0 = 011 for Register 00H). After a delay of T_INT, the IC repeats the adaptor detection process, as shown in Figure 15 and Figure 16.

Figure 15. Bad Adaptor Detection Circuit

Figure 16. Bad Adaptor Detection Scheme Flow Chart

9.4.1.3 Sleep Mode

The IC enters the low-power sleep mode if the VBUS pin voltage falls below the sleep-mode entry threshold, V_CSOUT+V_SLP, and VBUS is higher than the bad adaptor detection threshold, V_IN(MIN). This feature prevents draining the battery during the absence of V_BUS. During sleep mode, both the reverse blocking switch Q1 and PWM are turned off.

9.4.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)

During the charging process, if the input power source is not able to support the programmed or default charging current, the VBUS voltage will decrease. Once the VBUS drops to V_{IN_DPM} (default 4.52V), the charge current begins to taper down to prevent any further drop of VBUS. When the IC enters this mode, the charge current is lower than the set value and the special charger bit is set (B4 in Register 05H). This feature makes the IC compatible with adapters having different current capabilities.

9.4.2.1 Output Overvoltage Protection

The IC provides a built-in overvoltage protection to protect the device and other components against damage if the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage condition is detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT pin. Once V_(CSOUT) drops to the battery overvoltage exit threshold, the fault is cleared and charge process resumes.

9.4.2.2 Battery Detection at Power Up in DEFAULT Mode

bq24157 also has a unique battery detection scheme during the start up of the charger. At VBUS power up, bq24157 starts a 262-ms timer when exiting from short circuit mode to PWM charge mode. If the battery voltage is charged above the recharge threshold (V_OREG-VRCH) when the 262-ms timer expired, bq2157 will not consider the battery present; then stop charging, and go to high impedance mode immediately. However, if the battery voltage is still below the recharge threshold when the 262-ms timer expires, the charging process will continue as normal battery charging process.

9.4.2.3 Battery Short Protection

During the normal charging process, if the battery voltage is lower than the short-circuit threshold, V_SHORT, the charger operates in short circuit mode with a lower charge rate of I_SHORT.

9.4.2.4 Battery Detection in Host Mode

For applications with removable battery packs, the IC provides a battery absent detection scheme to reliably detect insertion or removal of battery packs.

During the normal charging process with host control, once the voltage at the CSOUT pin is above the battery recharge threshold, V_OREG - V_RCH, and the termination charge current is detected, the IC turns off the PWM charge and enables a discharge current, I_DETECT, for a period of t_DETECT, (262 ms typical) then checks the battery voltage. If the battery voltage is still above the recharge threshold after t_DETECT, the battery is present. On the other hand, if the battery voltage is below the battery recharge threshold, the battery is absent. Under this condition, the charge parameters (such as input current limit) are reset to the default values and charge resumes after a delay of T_INT. This function ensures that the charge parameters are reset whenever the battery is replaced.

9.5.1.1 Charge Profile

Once a good battery with voltage below the recharge threshold has been inserted and a good adapter is attached, the bq24157 enters charge mode. In charge mode, the IC has five control loops to regulate input voltage, input current, charge current, charge voltage and device junction temperature. During the charging process, all five loops are enabled and the one that is dominant takes control. The IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. Figure 17 (a) indicates a typical charge profile without input current regulation loop. It is the traditional CC/CV charge curve, while Figure 17(b) shows a typical charge profile when input current limiting loop is dominant during the constant current mode. In this case, the charge current is higher than the input current so the charge process is faster than the linear chargers. The input voltage threshold for DPM loop, input current limits, charge current, termination current, and charge voltage are all programmable using I²C interface.

Table 1. STAT Pin Summary

9.5.6.1 CE Bit (Charge Mode)

The CE bit in the control register is used to disable or enable the charge process. A low logic level (0) on this bit enables the charge and a high logic level (1) disables the charge.

9.5.6.2 RESET Bit

The RESET bit in the control register is used to reset all the charge parameters. Writing ‘1” to the RESET bit will reset all the charge parameters to default values except the safety limit register, and RESET bit is automatically cleared to zero once the charge parameters get reset. It is designed for charge parameter reset before charge starts and it is not recommended to set the RESET bit while charging or boosting are in progress.

9.5.6.3 OPA_Mode Bit

OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger if HZ_MODE is set to "0", refer to Table 2 for detail. When OPA_MODE=1 and HZ_MODE=0, the IC operates in boost mode.

Table 2. Operation Mode Summary

9.5.7.1 CD Pin (Charge Disable)

The CD pin is used to disable the charging process. When the CD pin is low, charge is enabled. When the CD pin is high, charge is disabled and the charger enters high impedance (Hi-Z) mode.

9.5.8.1 PWM Controller in Boost Mode

Similar to charge mode operation, in boost mode, the IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate output voltage at PMID pin (V_PMID). The voltage control loop is internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation with a wide load range and battery voltage range.

In boost mode, the input N-FET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle current limit is sensed through the internal sense FET for Q3. The cycle-by-cycle current limit threshold for Q3 is set to a nominal 1.0-A peak current. Synchronous operation is used in PWM mode to minimize power losses.

9.5.8.2 Boost Start Up

To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start up.

9.5.8.3 PFM Mode at Light Load

In boost mode, under light load conditions, the IC operates in pulse skipping mode (PFM mode) to reduce the power loss and improve the converter efficiency. During boosting, the PWM converter is turned off once the inductor current is less than 75mA; and the PWM is turned back on only when the voltage at PMID pin drops to about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between PWM and PFM mode.

9.5.8.4 Protection in Boost Mode

9.5.8.5 STAT Pin in Boost Mode

During normal boosting operation, the STAT pin behaves as a high impedance (open-drain) output. Under fault conditions, a 128-μs pulse is sent out to notify the host.

9.6.1.1 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 18. All I²C-compatible devices should recognize a start condition.

Figure 18. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 19). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 19) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established.

Figure 19. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 21). This releases the bus and stops the communication link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I²C logic from getting stuck in a bad state. Attempting to read data from register addresses not listed in this section will result in FFh being read out.

Figure 20. Acknowledge on the I²C Bus™

Figure 21. Bus Protocol

9.6.1.2 H/S Mode Protocol

When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the slave I2C logic from getting stuck in a bad state.

Attempting to read data from register addresses not listed in this section results in FFh being read out.

9.6.1.3 I²C Update Sequence

The IC requires a start condition, a valid I²C address, a register address byte, and a data byte for a single update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I²C address selects the IC. The IC performs an update on the falling edge of the acknowledge signal that follows the LSB byte.

For the first update, the IC requires a start condition, a valid I²C address, a register address byte, a data byte. For all consecutive updates, The IC needs a register address byte, and a data byte. Once a stop condition is received, the IC releases the I²C bus, and awaits a new start conditions.

Figure 22. Data Transfer Format in F/S Mode and H/S Mode

9.6.1.4 Slave Address Byte

The slave address byte is the first byte received following the START condition from the master device.

9.6.1.5 Register Address Byte

Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which contains the address of the register to be accessed. The IC contains five 8-bit registers accessible via a bidirectional I²C-bus interface. Among them, four internal registers have read and write access; and one has only read access.