SLUSBP5E March   2014  – July 2018 TPS92601-Q1 , TPS92602-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Typical Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope-Compensation Output Current
      3. 7.3.3 Boost-Current Limit
      4. 7.3.4 Oscillator and PLL
      5. 7.3.5 Control Loop Compensation
      6. 7.3.6 LED Open-Circuit Detection
      7. 7.3.7 Output Short-Circuit and Overcurrent Detection
      8. 7.3.8 Measuring LED Current During a Non-Failure Condition
      9. 7.3.9 LED Dimming Options
        1. 7.3.9.1 Analog Dimming
        2. 7.3.9.2 PWM Dimming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage and Overvoltage Shutdown
      2. 7.4.2 Overtemperature Shutdown
      3. 7.4.3 Device State Diagram
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Boost Regulator With Separate or Paralleled Channels
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency
          2. 8.2.1.2.2  Maximum Output-Current Set Point
          3. 8.2.1.2.3  Output Overvoltage-Protection Set Point
          4. 8.2.1.2.4  Duty Cycle Estimation
          5. 8.2.1.2.5  Inductor Selection
          6. 8.2.1.2.6  Rectifier Diode Selection
          7. 8.2.1.2.7  Output Capacitor Selection
          8. 8.2.1.2.8  Input Capacitor Selection
          9. 8.2.1.2.9  Current Sense and Current Limit
          10. 8.2.1.2.10 Switching MOSFET Selection
          11. 8.2.1.2.11 Loop Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Boost-to-Battery Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Switching Frequency
          2. 8.2.2.2.2  Maximum Output-Current Set Point
          3. 8.2.2.2.3  Output Overvoltage-Protection Set Point
          4. 8.2.2.2.4  Duty Cycle Estimation
          5. 8.2.2.2.5  Inductor Selection
          6. 8.2.2.2.6  Rectifier Diode Selection
          7. 8.2.2.2.7  Output Capacitor Selection
          8. 8.2.2.2.8  Input Capacitor Selection
          9. 8.2.2.2.9  Current Sense and Current Limit
          10. 8.2.2.2.10 Switching MOSFET Selection
          11. 8.2.2.2.11 Loop Compensation
        3. 8.2.2.3 TPS92602y-Q1 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.3.1 Fixed-Frequency PWM Control

Each boost controller uses an adjustable fixed-frequency peak-current-mode control. In a constant-current application, the device senses the output current across an external shunt resistor at the ISPx and ISNx pins, amplifies and level-shifts it to ground-reference, and compares it to the voltage applied on the ICTRLx pin by the primary error amplifier, which drives the COMPx pin. In a constant-voltage application, the device compares the output voltage through external resistors on the OVFBx pin to an internal 2.2-V voltage reference by a secondary error amplifier, which drives the COMPx pin. Depending on the chosen application, only one of the error amplifiers is active.

An internal oscillator initiates the turnon of the external boost-power NMOS switch. The device compares the error-amplifier output to the switch current sensed on the ISNSx pin. When the power-switch current reaches the level set by the COMPx voltage, the power NMOS switch turns off. The COMPx pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMPx pin voltage to a maximum level.