8.3.15 Fault Protections

The controller has several built-in fault protections. Most faults are subject to internal persistence filtering to avoid false-tripping due to noise or spurious glitches from external events. When a fault is detected and persists for the corresponding filter delay time, the device terminates and disables the PWM drive signal. No PWM activity occurs if the fault (pin faults for example) is detected at start-up . Table 3 lists all fault sources, persistence delays and the associated response (latching or auto-restart).

In the case of auto-restart (sometimes called hiccup-mode) faults, the device enters low-power mode for a time period of t_RESET(long) (or t_RESET(short) in the case of AC line UV fault and X-capacitor discharge), then discharges the VDD pin to the V_DD(reset) level, followed by a restart attempt. The device continues in a repeating shutdown-delay-restart loop until the fault is removed. Once the fault clears, the controller restarts automatically, there is no need to remove and re-apply AC input voltage to the system.

Latching faults do not allow any PWM restart attempts until the AC input voltage is removed. In this case the controller enters low-power mode. During low-power mode, the device regulates the VDD pin between two levels V_{DD(latch_hi)} and V_{DD(latch_lo)}, as given in Table 6, using the start-up HV current source. This regulation keeps the controller biased to maintain the latched fault condition as long as AC voltage is present at the input. When the device loses AC input voltage during latched-fault mode, the controller resets, and restarts when the AC input is re-applied.

If there is an open-feedback fault due to an open or short on the VSENSE pin or associated external resistor divider on the aux winding, the output voltage is protected against an over-voltage condition. If the open-feedback fault occurs before power-up, the fault will be detected by VSENSE pin- fault protection (see next section 9.3.16), and the controller will not generate any PWM drive signal. This prevents any possible output OV due to this open-feedback fault condition. If the open-feedback occurs after power-up, when the power stage is already operating, the open-feedback condition can cause Vout to increase. In this case, the VDD level will also increase in proportion to Vout (they will track based on the Flyback transformer turns ratio). When the VDD rail reaches the V_DD(ovp) protection threshold, the PWM will be disabled, and the controller will go to fault mode, as described above. The V_DD(ovp) protection is used as an indirect back-up OV protection mechanism for the main output under running open-feedback fault conditions. The level of output OV depends on the ratio of the normal VDD regulation level to the V_DD(ovp) level. Note that UCC28630/1/2/3 use V_DD(ovp) trip level of 17.5 V nominal, whereas the UCC28634 uses a lower V_DD(ovp) of 14.85 V nominal, to ensure a lower/tighter level of output OV under VSENSE open-feedback conditions. As a result, the user must be careful to choose the number of turns in the transformer aux winding to ensure that the normal VDD regulation is below the V_DD(ovp) protection level, to avoid false-triggering of the V_DD(ovp) protection.