SLUSC72C
May 2015 – July 2024
UCC27201A-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Timing Diagrams
5.8
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Input Stages
6.3.2
UVLO (Under Voltage Lockout)
6.3.3
Level Shift
6.3.4
Boot Diode
6.3.5
Output Stages
6.4
Device Functional Modes
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Input Threshold Type
7.2.2.2
VDD Bias Supply Voltage
7.2.2.3
Peak Source and Sink Currents
7.2.2.4
Propagation Delay
7.2.2.5
Power Dissipation
7.2.3
Application Curves
8
Power Supply Recommendations
9
Layout
9.1
Layout Guidelines
9.2
Layout Example
10
Device and Documentation Support
10.1
Third-Party Products Disclaimer
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
Support Resources
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
1
Features
AEC-Q100 qualified for automotive applications: device temperature grade 1
–40°C to +150°C junction temperature range
Negative voltage handling on HS: -18V
Drives two N-channel MOSFETs in high-side/low-side configuration
Maximum boot voltage: 120V
Maximum VDD voltage: 20V
On-chip 0.65V V
F
, 0.65Ω R
D
bootstrap diode
22ns propagation delay times
3A sink, 3A source output currents
8ns rise and 7ns fall time with 1000pF load
1ns delay matching
Undervoltage lockout for high-side and low-side driver
Offered in 8-pin
PowerPad™
SOIC-8 (DDA)