10.1 Layout Guidelines

In order to increase the reliability and feasibility of the project it is recommended to adhere to the following guidelines for PCB layout. In Figure 32, a typical 5-V/2-A USB adapter design schematic is shown in Figure 32.

• Minimize stray capacitance on the VS node. Place the voltage sense resistors (R_S1 and R_S2 in Figure 24) close to the VS pin.
• Arrange the components to minimize the loop areas of the switching currents as much as possible. These areas include such loops as the transformer primary winding current loop (a), the MOSFET gate-drive loop (b), the primary snubber loop (c), the auxiliary winding loop (d) and the secondary output current loop (e). In practice, trade-offs may have to be made. Loops with higher current should be minimized with higher priority. As a rule of thumb, the priority goes from high to low as (a) – (e) – (c) – (d) – (b).
• The R_LC resistor location is critical. To avoid any dv/dt induced noise (for example MOSFET drain dv/dt) coupled onto this resistor, it is better to place R_LC closer to the controller and avoid nearby the MOSFET.
• To improve thermal performance increase the copper area connected to GND pins.

10.2 Layout Example

Figure 33 demonstrates a 10-W, 5-V/2-A, layout with trade-offs to minimize the loops while effectively placing components and tracks for low noise operation on a single-layer printed circuit board. In addition to the consideration of minimal loops, one another layout guideline is always to use the device GND as reference point. This applies to both power and signal to return to the device GND pin (pin 5).