Selecting FETs for a design is an iterative process. To meet the power requirements of this design, we select 75V, 120A FETs, from Fairchild, part number FDP032N08. These FETs have the following characteristics.

Equation 75.

Equation 76.

Calculate average FET C_OSS (C_{OSS_QE_AVG}) based on the data sheet parameters for C_OSS (C_{OSS_SPEC}), and drain to source voltage where C_{OSS_SPEC} was measured (V_{ds_spec}), and the maximum drain to source voltage in the design (V_dsQE) that will be applied to the FET in the application.

The voltage across FET QE and QF when they are of isf:

Equation 77.

The voltage where FET C_OSS is specified and tested in the FET data sheet:

Equation 78.

The specified output capacitance from FET data sheet is:

Equation 79.

The average QE and QF C_OSS [2] is calculated using Equation 80:

Equation 80.

The QE and QF RMS current are:

Equation 81.

To estimate FET switching loss the V_g vs. Q_g curve from the FET data sheet needs to be studied. First the gate charge at the beginning of the miller plateau needs to be determined (QE_{MILLER_MIN}) and the gate charge at the end of the miller plateau (QE_{MILLER_MAX}) for the given V_DS.

The maximum gate charge at the end of the miller plateau is:

Equation 82.

The minimum gate charge at the beginning of the miller plateau is:

Equation 83.

Equation 84.

Estimated FET V_ds rise and fall time using Equation 85:

Equation 85.

Estimate QE and QF FET Losses (P_QE) using Equation 86:

Equation 86.

Equation 87.

Recalculate the power budget using Equation 88.

Equation 88.