For best results in the voltage loop, TI recommends using a Type 2 or Type 3 compensation network (Figure 7-6). A Type 2 compensation network does not require passive components C_Z2 and R_Z2. Type 1 compensation is not versatile enough for a phase-shifted full bridge. When evaluating the COMP pin for best results, TI recommends placing a 1-kΩ resistor between the scope probe and the COMP pin of the UCC2895x-Q1.

Compensating the feedback loop can be accomplished by properly selecting the feedback components (R5, C1 and C2). These components are placed as close as possible to pin 3 and 4 of the controller. A Type 2 compensation network is designed in this example.

Calculate load impedance at 10% load (R_LOAD) :

Approximate control to output transfer function (G_CO(f)) as a function of frequency:

Calculate double pole frequency of G_CO(f):

Calculate angular velocity:

Compensate the voltage loop with Type 2 feedback network. The following transfer function is the compensation gain as a function of frequency (G_C(f)):

Calculate voltage loop feedback resistor (R5) based on the crossing the voltage loop (f_C) over at a 10^th of the double pole frequency (f_PP):

The standard resistor selcted for R5 is 27.4 kΩ.

Calculate the feedback capacitor (C2) to give added phase at crossover:

The standard capacitance value (C2) selected for the design is 5.6 nF.

Put a pole at two times f_C:

The standard capacitance value (C1) selected for the design is 560 pF.

Use Equation 126 to calculate the loop gain as a function of frequency (T_V(f)) in dB.

Plot a theoretical loop gain and phase to graphically confirm loop stability. The theoretical loop gain crosses over at roughly 3.7 kHz with a phase margin of greater than 90 degrees.

where

• loop gain (T_VdB(f))
• loop phase (ΦT_V(f))

To limit overshoot during the power up sequence, the UCC2895x-Q1 has a soft-start function (SS, Pin 5). In this application the soft-start time is 15 ms (t_SS).

The standard capacitor (C_SS) selected for this design is 150 nF.

This application presents a fixed delay approach to achieving ZVS from 100% load down to 50% load. Adaptive delays can be generated by connecting the ADEL and ADELEF pins to the CS pin as shown in Figure 7-8 .

When the converter is operating below 50% load, the converter operates in valley switching. To achieve zero voltage switching on switch node of QB_d, the turn-on (t_ABSET) delays of FETs QA and QB must be initially set based on the interaction of L_S and the theoretical switch node capacitance. The following equations are used to set t_ABSET initially.

Equate shim inductance to two times C_OSS capacitance using Equation 129:

Calculate tank frequency using Equation 130:

Set initial t_ABSET delay time and adjust as necessary.

The resistor divider formed by R_A and R_AHI programs the t_ABSET, t_CDSET delay range of the controller. The standard resistor value R_AHI selected is 8.25 kΩ.

t_ABSET can be programmed between 30 ns to 1000 ns.

The voltage at the ADEL input of the controller (V_ADEL) must be set with R_A based on the following conditions:

• If t_ABSET > 155 ns, set V_ADEL = 0.2 V. t_ABSET can be programmed between 155 ns and 1000 ns.
• If t_ABSET ≤ 155 ns, set V_ADEL = 1.8 V. t_ABSET can be programmed between 29 ns and 155 ns.

Based on V_ADEL selection, calculate R_A:

The closest standard resistor value for R_A selected is 348 Ω.

Recalculate V_ADEL based on resistor divider selection:

Resistor R_AB programs t_ABSET. Variable CS is the voltage at the CS pin with respect to ground and ratio K_A was calculated in Equation 5:

The standard resistor value for R_AB selected for the design is 30.1 kΩ.

Initially, set the QC and QD turn-on delays (t_CDSET) for the same delay as the QA and QB turn-on delays (Pin 6). The following equations program the QC and QD turn-on delays (t_CDSET) by properly selecting resistor R_DELCD (Pin 7).

Resistor R_CD programs t_CDSET:

The standard resistor R_CD selected for this design is 30.1 kΩ.

There is a programmable delay for the turnoff of FET QF after FET QA turnoff (t_AFSET) and the turnoff of FET QE after FET QB turnoff (t_BESET). Set these delays to 50% of t_ABSET to ensure that the appropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large, it causes OUTE and OUTF not to overlap correctly and creates excess body diode conduction on FETs QE and QF.

The resistor divider formed by R_AEF and R_AEFHI programs the t_AFSET and t_BESET delay range of the controller. The standard resistor value selected for R_AEFHI is 8.25 kΩ.

The voltage at the ADELEF pin of the controller (V_ADELEF) needs to be set with R_AEF based on the following conditions.

• If t_AFSET < 170 ns set V_ADEL = 0.2 V, t_ABSET can be programmed between 32 ns and 170 ns.
• If t_ABSET > or = 170 ns set V_ADEL = 1.7 V, t_ABSET can be programmed between 170 ns and 1100 ns.

Based on V_ADELEF selection, calculate R_AEF:

The closest standard resistor value for R_AEF is 4.22 kΩ.

Recalculate V_ADELEF based on resistor divider selection:

The following equation was used to program t_AFSET and t_BESET by properly selecting resistor R_EF.

The standard resistor value selected for R_EF is 14 kΩ.

Resistor R_TMIN programs the minimum on time (t_MIN) that the UCC2895x-Q1 (Pin 9) can demand before entering burst mode. If the UCC2895x-Q1 controller tries to demand a duty cycle on time of less than t_MIN the power supply goes into burst mode operation. For this design set the minimum on-time (t_MIN) to 75 ns.

Set the minimum on-time by selecting R_TMIN :

The standard resistor value for R_TMIN is 13 kΩ.

A resistor from the RT pin to ground sets the converter switching frequency calculated in Equation 142.

The standard resistor value selected for R_T is 61.9 kΩ.

The UCC2895x-Q1 provides slope compensation. The amount of slope compensation is set by the resistor R_SUM. As suggested earlier, set the slope compensation ramp to be half the inductor current ramp downslope (inductor current ramp during the off time), reflected through the main transformer and current sensing networks as explained earlier in Section 6.3.11.

Calculate required slope compensation ramp:

The magnetizing current of the power transformer provides part of the slope compensation ramp. The slope of this current is calculated using Equation 144 where V_INHU is the minimum voltage for V_OUT holdup purposes. It is the voltage at which the converter is operating at the maximum dudy cycle (D_MAX) while maintaining V_OUT:

Calculate the required compensating ramp:

The value for the resistor, R_SUM, may be found from the graph in Figure 6-10, calculated from rearranged versions of Equation 13, or calculated by Equation 13, depending on whether the controller is operating in current mode or voltage control mode. This design uses current mode control and Equation 146 is rearranged and evaluated:

Confirm that the 300 mV allowed for the slope compensation ramp is sufficient when choosing R_CS in Equation 100.

To increase efficiency at lighter loads the UCC2895x-Q1 is programmed (Pin 12, DCM) under light-load conditions to disable the synchronous FETs on the secondary side of the converter (Q_E and Q_F). This threshold is programmed with resistor divider formed by R_DCMHI and R_DCM. This DCM threshold needs to be set at a level before the inductor current goes discontinuous. Equation 148 sets the level at which the synchronous rectifiers are disabled at roughly 15% load current.

The standard resistor value selected for R_DCM is 1 kΩ.

Calculate resistor value R_DCMHI.

The standard resistor value for R_DCMHI is 16.9 kΩ.