SLUSD04C july   2018  – april 2023 BQ25150

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Key Default Settings
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Linear Charger and Power Path
        1. 9.3.1.1 Battery Charging Process
          1. 9.3.1.1.1 Pre-Charge
          2. 9.3.1.1.2 Fast Charge
          3. 9.3.1.1.3 Pre-Charge to Fast Charge Transitions and Charge Current Ramping
          4. 9.3.1.1.4 Termination
        2. 9.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 9.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
        4. 9.3.1.4 Battery Supplement Mode
      2. 9.3.2  Protection Mechanisms
        1. 9.3.2.1 Input Over-Voltage Protection
        2. 9.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 9.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 9.3.2.4 Battery Short and Over Current Protection
        5. 9.3.2.5 PMID Short Circuit
        6. 9.3.2.6 Maximum Allowable Charging Current (IMAX)
      3. 9.3.3  ADC
        1. 9.3.3.1 ADC Operation in Active Battery Mode and Low Power Mode
        2. 9.3.3.2 ADC Operation When VIN Present
        3. 9.3.3.3 ADC Measurements
        4. 9.3.3.4 ADC Programmable Comparators
      4. 9.3.4  VDD LDO
      5. 9.3.5  Load Switch / LDO Output and Control
      6. 9.3.6  PMID Power Control
      7. 9.3.7  MR Wake and Reset Input
        1. 9.3.7.1 MR Wake or Short Button Press Functions
        2. 9.3.7.2 MR Reset or Long Button Press Functions
      8. 9.3.8  14-Second Watchdog for HW Reset
      9. 9.3.9  Faults Conditions and Interrupts ( INT)
        1. 9.3.9.1 Flags and Fault Condition Response
      10. 9.3.10 Power Good ( PG) Pin
      11. 9.3.11 External NTC Monitoring (TS)
        1. 9.3.11.1 TS Thresholds
      12. 9.3.12 External NTC Monitoring (ADCIN)
      13. 9.3.13 I2C Interface
        1. 9.3.13.1 F/S Mode Protocol
    4. 9.4 Device Functional Modes
      1. 9.4.1 Ship Mode
      2. 9.4.2 Low Power
      3. 9.4.3 Active Battery
      4. 9.4.4 Charger/Adapter Mode
      5. 9.4.5 Power-Up/Down Sequencing
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input (IN/PMID) Capacitors
        2. 10.2.2.2 VDD, LDO Input and Output Capacitors
        3. 10.2.2.3 TS
        4. 10.2.2.4 IMAX Selection
        5. 10.2.2.5 Recommended Passive Components
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

8.6 Timing Requirements

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
BATTERY CHARGE TIMERS
tMAXCHGCharge safety timerProgrammable range180720min
tPRECHGPrecharge safety timer0.25 * tMAXCHG
WATCHDOG TIMERS
tWATCHDOG_SWSW Watchdog timer2550s
tHW_RESET_WDHW reset watchdog timerHWRESET_14S_WD = 114s
LDO
tON_LDOTurn ON time100mA load, to 90% VLDO500µs
tOFF_LDOTurn OFF time100mA load, to 10% VLDO30µs
tPMID_LDO_DELAYDelay between PMID and LDO enable during power upStartup20ms
PUSHBUTTON TIMERS (/MR)
tWAKE1WAKE1 Timer. Time from /MR falling edge to INT being asserted.MR_WAKE1_TIMER = 0106125144ms
MR_WAKE1_TIMER = 1425500575ms
tWAKE2WAKE2 Timer. Time from /MR falling edge to INT being asserted.MR_WAKE2_TIMER = 00.8511.15s
MR_WAKE2_TIMER = 11.722.3s
tRESET_WARNRESET_WARN Timer. Time prior to HW RESET or entering shipmode with MR pressMR_RESET_WARN = 000.420.50.58s
MR_RESET_WARN = 010.8511.15s
MR_RESET_WARN = 101.271.51.73s
MR_RESET_WARN = 111.722.3s
tHW_RESETHW RESET Timer. Time from /MR falling edge to HW Reset or PMID falling for shipmode entryMR_HW_RESET = 003.444.6s
MR_HW_RESET = 016.889.2s
MR_HW_RESET = 108.51011.5s
MR_HW_RESET = 1111.91416.1s
tRESTART(AUTOWAKE)RESTART Timer. Time from /MR HW Reset to PMID power upAUTOWAKE = 000.520.60.68s
AUTOWAKE = 011.051.21.35s
AUTOWAKE = 102.112.42.69s
AUTOWAKE = 114.455.6s
PROTECTION
tDGL_SLPDeglitch time for supply rising above VSLP + VSLP_HYS120µs
tDGL_OVPDeglitch time for VOVP ThresholdVIN falling below VOVP32ms
tDGL_OCPBattery OCP deglitch time30µs
tREC_SCRecovery time, BAT Short Circuit during Discharge Mode250ms
tRETRY_SCRetry window for PMID or BAT short circuit recovery2s
tDGL_SHTDWNDeglitch time, Thermal shutdownTJ rising above TSHUTDOWN10µs
I2C INTERFACE
tWATCHDOGI2C interface reset timer for hostWhen enabled50s
tI2CRESETI2C interface inactive reset timer500ms
INPUT PINS (/CE and /LP)
tLP_EXIT_I2CTime for device to exit Low-power mode and allow I2C communicationVIN = 0V.1ms