SLUSD37 Data sheet

SLUSD37E October 2017 – November 2019 UCC28056

PRODUCTION DATA.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE
V_CCStart	Turn-on threshold	VCC Rising		10.65	11	V
V_CCStop	Turn-off threshold	VCC Falling	8.5	8.85	9.2	V
V_CCHyst	UVLO Hysteresis (V_{CCStart -}V_CCStop) ⁽¹⁾		1.5			V
T_UVLOBlk	Turn-OFF Blanking Time		27	35	42	µs
SUPPLY CURRENT
I_{CC_Startup}	Current consumption before startup	VCC = V_CCStart-200mV, T_A < 110℃			46	µA
I_{CC_FAULT}	Current consumption during fault condition	VCC = 12V			130	µA
I_{CC_BSTOFF}	Current consumption during Burst OFF period	VCC = 12V			132	µA
I_{CC_RUN}	Operating current with DRV pin unloaded	VCC = 12V		1.8	2.2	mA
GATE DRIVE
V_DRLow	DRV output low voltage	I_DR = 100mA			0.9	V
V_DRHigh	DRV output voltage high level, limited	VCC = 25V, I_DR = -10mA	10	13.7	15	V
V_DRHighMin	DRV minimum high voltage level	VCC = V_CCStop + 200 mV, I_DR = -8mA	8			V
R_DRH	DRV, Pull-up resistance	T_A = -40°C to 125°C, I_DR = -8mA, VCC=12V		9.7	16	Ω
R_DRL	DRV, Pull-down resistance	T_A = -40°C to 125°C, I_DR = 100mA	2.0	4.6	9	Ω
t_R	Rise Time	CLOAD=1nF, DRV=1V to 6V, VCC=12V	10	34	61	ns
t_F	Fall Time	CLOAD=1nF, DRV=6V to 1V, VCC=12V	4	15	40	ns
Isource	Source peak current on DRV Pin ⁽¹⁾			-0.7		A
Isink	Sink peak current on DRV Pin ⁽¹⁾			1		A
R_DG0	DRV to GND resistance value to select T_ZCDR0 ⁽¹⁾		130	200		kΩ
R_DG1	DRV to GND resistance value to select T_ZCDR1 ⁽¹⁾		81.18	82	82.82	kΩ
R_DG2	DRV to GND resistance value to select T_ZCDR2 ⁽¹⁾		61.38	62	62.62	kΩ
R_DG3	DRV to GND resistance value to select T_ZCDR3 ⁽¹⁾		42.57	43	43.43	kΩ
R_DG4	DRV to GND resistance value to select T_ZCDR4 ⁽¹⁾		26.73	27	27.27	kΩ
R_DG5	DRV to GND resistance value to select T_ZCDR5 ⁽¹⁾		17.82	18	18.18	kΩ
R_DG6	DRV to GND resistance value to select T_ZCDR6 ⁽¹⁾		12.87	13	13.13	kΩ
R_DG7	DRV to GND resistance value to select T_ZCDR7 ⁽¹⁾		9	9.1	9.2	kΩ
T_DGSmpl	Time needed to detect R_DG value.	T_A < 85℃	3.95	4.4	4.95	ms
V_DGClmp	Maximum voltage that will be applied on DRV pin while detecting R_DG value.		1	1.05	1.1	V
Error Amplifier
V_OSReg	Feedback voltage reference		2.45	2.5	2.55	V
I_OSBias	ISNS pin bias current	V_OS = V_OSReg	-100		100	nA
g_M	Error Amplifier Transconductance Gain	\|V_OS-V_OSReg\| < DSuThs		50		µS
g_MNL	Error Amplifier Transconductance Gain for large error	\|V_OS-V_OSReg\| > DSuThs		300		µS
DSuThs	Non-Linear Gain Threshold		67			mV
R_CODisch	Internal COMP to GND resistance when in STOPb state.		4.3	5	5.7	kΩ
V_COClmp	COMP pin internal high clamp voltage		5.5	5.6	5.71	V
V_COSat	COMP pin internal low clamp voltage ⁽¹⁾			0		V
I_COMin	COMP Maximum Source Current			-120		µA
I_COMax	COMP Maximum Sink Current			120		µA
Line Voltage Feed-Forward
T_HLinMax	Line peak sampling window ⁽¹⁾	While switching	11	12.3	13.6	ms
V_FF0Rise	Comparator rising threshold switching from G_FF0 to G_FF1 ⁽¹⁾			0.348		V
V_FF1Rise	Comparator rising threshold switching from G_FF1 to G_FF2 ⁽¹⁾			0.406		V
V_FF2Rise	Comparator rising threshold switching from G_FF2 to G_FF3 ⁽¹⁾			0.473		V
V_FF3Rise	Comparator rising threshold switching from G_FF3 to G_FF4 ⁽¹⁾			0.552		V
V_FF4Rise	Comparator rising threshold switching from G_FF4 to G_FF5 ⁽¹⁾			0.644		V
V_FF5Rise	Comparator rising threshold switching from G_FF5 to G_FF6 ⁽¹⁾			0.751		V
V_FF6Rise	Comparator rising threshold switching from G_FF6 to G_FF7 ⁽¹⁾			0.875		V
V_FF0Fall	Comparator falling threshold switching from G_FF1 to G_FF0 ⁽¹⁾	Peak value of V_InSynth within T_HLinMax Window		0.331		V
V_FF1Fall	Comparator falling threshold switching from G_FF2 to G_FF1 ⁽¹⁾	Peak value of V_InSynth within T_HLinMax Window		0.386		V
V_FF2Fall	Comparator falling threshold switching from G_FF3 to G_FF2 ⁽¹⁾	Peak value of V_InSynth within T_HLinMax Window		0.45		V
V_FF3Fall	Comparator falling threshold switching from G_FF4 to G_FF3 ⁽¹⁾	Peak value of V_InSynth within T_HLinMax Window		0.524		V
V_FF4Fall	Comparator falling threshold switching from G_FF5 to G_FF4 ⁽¹⁾	Peak value of V_InSynth within T_HLinMax Window		0.612		V
V_FF5Fall	Comparator falling threshold switching from G_FF6 to G_FF5 ⁽¹⁾	Peak value of V_InSynth within T_HLinMax Window		0.713		V
V_FF6Fall	Comparator falling threshold switching from G_FF7 to G_FF6 ⁽¹⁾	Peak value of V_InSynth within T_HLinMax Window		0.832		V
G_FF0	Line Feed-Forward gain level 0 ⁽¹⁾			1
G_FF1	Line Feed-Forward gain level 1 ⁽¹⁾			0.735
G_FF2	Line Feed-Forward gain level 2 ⁽¹⁾			0.541
G_FF3	Line Feed-Forward gain level 3 ⁽¹⁾			0.398
G_FF4	Line Feed-Forward gain level 4 ⁽¹⁾			0.292
G_FF5	Line Feed-Forward gain level 5 ⁽¹⁾			0.215
G_FF6	Line Feed-Forward gain level 6 ⁽¹⁾			0.158
G_FF7	Line Feed-Forward gain level 7 ⁽¹⁾			0.116
Maximum ON Time
T_ONMAX0	Maximum ON time when G_FF = G_FF0		12.1	12.8	13.2	µs
T_ONMAX1	Maximum ON time when G_FF = G_FF1		10.42	10.98	11.28	µs
T_ONMAX2	Maximum ON time when G_FF = G_FF2		8.85	9.41	9.64	µs
T_ONMAX3	Maximum ON time when G_FF = G_FF3		7.59	8.07	8.32	µs
T_ONMAX4	Maximum ON time when G_FF = G_FF4		6.52	6.92	7.18	µs
T_ONMAX5	Maximum ON time when G_FF = G_FF5		5.56	5.93	6.16	µs
T_ONMAX6	Maximum ON time when G_FF = G_FF6		4.73	5.09	5.28	µs
T_ONMAX7	Maximum ON time when G_FF = G_FF7		4.07	4.36	4.57	µs
Burst Mode Operation See Device Comparison Table
Zero Current Detection and Valley Synch
V_ZcdVinHyst	ZcdVin Comparator hysteresis ⁽¹⁾		12	19	26	mV
T_DCHVinMin	ZcdVin Comparator blanking from DRV falling edge ⁽¹⁾		250	358	467	ns
T_ZCDTo	If no negative transitions on Vin comparator for this period then do not wait for valleys		2.035	2.4	3.0	µs
T_ZCDR0	Minimum ZCD to DRV delay.	From V_ZC < V_InSynth to DRV = 6V, C_DR = 1nF, Fres = 1.2MHz, R_DG = R_DG0		170	235	ns
ΔT_ZCDR1	T_ZCDR1 = T_ZCDR0 + ΔT_ZCDR1⁽¹⁾	R_DG = R_DG1	34.6	45.5	58.5	ns
ΔT_ZCDR2	T_ZCDR2 = T_ZCDR0 + ΔT_ZCDR2⁽¹⁾	R_DG = R_DG2	76	90	107	ns
ΔT_ZCDR3	T_ZCDR3 = T_ZCDR0 + ΔT_ZCDR3⁽¹⁾	R_DG = R_DG3	114	130	147	ns
ΔT_ZCDR4	T_ZCDR4 = T_ZCDR0 + ΔT_ZCDR4⁽¹⁾	R_DG = R_DG4	157	175	193	ns
ΔT_ZCDR5	T_ZCDR5 = T_ZCDR0 + ΔT_ZCDR5⁽¹⁾	R_DG = R_DG5	229	255	281	ns
ΔT_ZCDR6	T_ZCDR6 = T_ZCDR0 + ΔT_ZCDR6⁽¹⁾	R_DG = R_DG6	301	335	369	ns
ΔT_ZCDR7	T_ZCDR7 = T_ZCDR0 + ΔT_ZCDR7⁽¹⁾	R_DG = R_DG7	373	415	457	ns
V_DDAmpl	Amplitude of 500 kHz sinewave signal on ZCD/CS pin needed to trigger knee detector		25			mV
T_DCHDDMin	Knee point detector blanking period ⁽¹⁾	Measured from falling edge of DRV pulse		1.5		µs
Fault Protection
T_LongFlt	Long Fault Duration ⁽¹⁾			1		s
Line Brown-In Protection
V_ZCBoRise	Brown-out Protection Threshold when in Stopb state	Peak cycle average voltage on ZCD/CS Pin.	0.282	0.3	0.318	V
I_ZCBias	ZCD/CS Pin Bias Current ⁽¹⁾	V_ZC = V_ZCBoFall	-100		100	nA
Over-Current Protection
V_ZCOcp1	ZCD/CS First Level over-current protection threshold		450	500	550	mV
V_ZCOcp2	ZCD/CS Second Level over-current protection threshold		670	750	825	mV
T_Ocp1Blk	ZCD/CS blanking time from DRV rising edge to Enable Ocp1 Comparator Output ⁽¹⁾			450		ns
T_Ocp2Blk	ZCD/CS blanking time from DRV rising edge to Enable Ocp2 Comparator Output ⁽¹⁾			250		ns
T_OcpDrvDel	ZCD/CS crossing V_OcpxTh to DRV falling edge.			56	120	ns
T_DCHMax0	Max duration of T_DCHb state if no ZCD signal detected. After no OCPx Events ⁽¹⁾			250		µS
T_DCHMax1	Max duration of T_DCHb state if no ZCD signal detected. After one OCPx Events ⁽¹⁾			500		µS
T_DCHMax2	Max duration of T_DCHb state if no ZCD signal detected. After two consecutive OCPx Events ⁽¹⁾			1000		µS
Output Over-Voltage Protection See Device Comparison Table
Thermal Protection
T_TSDRise	Thermal Shutdown Rising Threshold ⁽¹⁾	While switching	135	145	155	°C
T_TSDFall	Thermal Shutdown Falling Threshold ⁽¹⁾	While not switching	95	105	115	°C
T_TSDHyst	T_TSDRise - T_TSDFall ⁽¹⁾		38	40	42	°C

(1) Not tested in production. Ensured by design.