SLUSD48C July   2018  – March 2022 UCC24624

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description, Continued
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Synchronous Rectifier Control
      3. 8.3.3 Turn-off Threshold Adjustment
      4. 8.3.4 Noise Immunity
        1. 8.3.4.1 On-Time Blanking
        2. 8.3.4.2 Off-Time Blanking
        3. 8.3.4.3 Two-Channel Interlock
        4. 8.3.4.4 SR Turn-on Re-arm
        5. 8.3.4.5 Adaptive Turn-on Delay
      5. 8.3.5 Gate Voltage Clamping
      6. 8.3.6 Standby Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Run Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MOSFET Selection
        2. 9.2.2.2 Snubber Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks

7.6 Timing Requirements

At VVDD = 12 VDC, CVG1 = CVG2 = 0 pF, CREG = 2.2 µF, VVD1 = VVD2 = 0 V, –40°C ≤ TJ = TA ≤ +125°C, all voltages are with respect to PGND, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
GATE DRIVER
tdVGON SR turn-on propagation delay, for both channels VVD1, VVD2 moves from 4.7 V to -0.5 V in 5 ns 110 155 225 ns
tdVGOFF SR turn-off propagation delay, for both channels VVD1, VVD2 moves from -0.5 V to 4.7 V in 5 ns 5.5 23 40 ns
trVG VVG1, VVG2 rise time 10% to 90%, VVDD = 12 V, CVG = 6.8 nF 13 23 40 ns
tfVG VVG1, VVG2 fall time 90% to 10%, VVDD = 12 V, CVG = 6.8 nF 19 35 ns
BLANKING TIME
tONMIN On-time blanking 325 475 625 ns
tMGPU Minimum gate pullup time IVG1, IVG2 = 1.5 A 180 275 370 ns
tOFFMIN Off-time blanking 440 650 855 ns
STANDBY
tSTBY_DET Standby mode detection-time 5.5 7.5 10 ms
fSLEEP Average frequency entering standby mode 6.55 9 12.2 kHz
fWAKE Average frequency coming out of standby mode 11.5 15.6 21 kHz