SLUSD48C
July 2018 – March 2022
UCC24624
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description, Continued
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Power Management
8.3.2
Synchronous Rectifier Control
8.3.3
Turn-off Threshold Adjustment
8.3.4
Noise Immunity
8.3.4.1
On-Time Blanking
8.3.4.2
Off-Time Blanking
8.3.4.3
Two-Channel Interlock
8.3.4.4
SR Turn-on Re-arm
8.3.4.5
Adaptive Turn-on Delay
8.3.5
Gate Voltage Clamping
8.3.6
Standby Mode
8.4
Device Functional Modes
8.4.1
UVLO Mode
8.4.2
Standby Mode
8.4.3
Run Mode
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
MOSFET Selection
9.2.2.2
Snubber Design
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.1.1.1
Custom Design With WEBENCH® Tools
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
1
Features
230-V VD pins rating
23-ns turn-off delay to support LLC operating above resonant frequency and up to 625-kHz switching frequency
Proportional gate drive to extend the SR conduction time
Adjustable turn-off threshold for minimum body diode conduction
Automatic standby mode detection with 180 µA of low standby current
Wide 4.25-V to 26-V VDD operation range with internal clamp
Adaptive turn-on delay for better DCM ring rejection
Two-channel interlock to prevent shoot-through
Integrated 1.5-A source and 4-A sink capability gate driver for N-channel MOSFETs
8-pin SOIC package