SLUSD48C July   2018  – March 2022 UCC24624

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description, Continued
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Synchronous Rectifier Control
      3. 8.3.3 Turn-off Threshold Adjustment
      4. 8.3.4 Noise Immunity
        1. 8.3.4.1 On-Time Blanking
        2. 8.3.4.2 Off-Time Blanking
        3. 8.3.4.3 Two-Channel Interlock
        4. 8.3.4.4 SR Turn-on Re-arm
        5. 8.3.4.5 Adaptive Turn-on Delay
      5. 8.3.5 Gate Voltage Clamping
      6. 8.3.6 Standby Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Run Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MOSFET Selection
        2. 9.2.2.2 Snubber Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks

9.2.3 Application Curves

The typical operation waveforms, as well as the efficiency performance are summarized in following sections.

  • CH1 = VG1(TP4), CH3 = Q1 drain (TP2), CH2 = VG2(TP5), CH4 = Q1 drain (TP3)
GUID-1F5E94DC-31A6-4B80-9DD8-19CF09C4DB87-low.jpgFigure 9-2 VIN = 340 V, IOUT = 0 A, No Gate Drive Under Light Load (VG1, VG2)
GUID-B28D8E20-F732-41A2-99FB-0217504B2FDE-low.jpgFigure 9-4 VIN = 340 V, IOUT = 10 A Full Load
GUID-680B52D9-428B-4E58-80E5-6D216C52339A-low.jpgFigure 9-3 VIN = 340 V, IOUT = 0.3 A, LLC is Operating In Burst Mode
GUID-DE6C786E-F0A9-41BD-91F7-A1163E04EF29-low.jpgFigure 9-5 VIN = 390 V, IOUT = 0 A, No Gate Drive Under Light Load (VG1, VG2)
GUID-13BA9E4A-9B66-449D-B5B1-E236F9B807A0-low.jpgFigure 9-6 VIN = 390 V, IOUT = 0.3 A, LLC is Operating In Burst Mode
GUID-1723A358-F24E-43AD-AFE2-63D8565FAB8C-low.jpgFigure 9-8 VIN = 410 V, IOUT = 0 A, No Gate Drive Under Light Load (VG1, VG2)
GUID-4DB4A312-4263-42AA-956C-5794490B5FF4-low.jpgFigure 9-10 VIN = 410 V, IOUT = 10 A Full Load
GUID-531C7436-B574-4118-B039-6C57ACE48FDA-low.jpgFigure 9-7 VIN = 390 V, IOUT = 10 A Full Load
GUID-68D874B2-9A29-486F-B83E-4F10123CC314-low.jpgFigure 9-9 VIN = 410 V, IOUT = 0.3 A, LLC is Operating In Burst Mode
GUID-4F138CA5-D43C-41CB-ABBB-4422628ECBE6-low.gifFigure 9-11 VIN = 390 V, Power Converter System Efficiency Using SR FETs