SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
The SYSCFG2 register is the second system configuration register. This register contains bits associated with enabling fault handling for both channels and configuring the fault timer. Figure 7-23 shows SYSCFG2. Table 7-8 describes SYSCFG2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IFT | CH2TSFL | CH2HSILIMFL | CH2LSILIMFL | CH1TSFL | CH1HSILIMFL | CH1LSILIMFL | |
R/W - 00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | IFT | R/W | 00 | IFT sets the counter limit for the fault timer as shown below. 00 = 3.6 ms fault timer 01 = 7.2 ms fault timer 10 = 14.4 ms fault timer 11 = 28.8 ms fault timer |
5 | CH2TSFL | R/W | 0 | Channel 2 thermal shutdown fault response 0 = Channel 2 auto-restarts based on internal temperature hysteresis. 1 = Channel 2 is latched off; CH2EN bit is reset and channel 2 is disabled until the CH2EN bit is programmed high by SPI command. |
4 | CH2HSILIMFL | R/W | 0 | Channel 2 high-side FET current limit fault response 0 = Channel 2 auto-restarts after the ILIM fault timer has expired. 1 = Channel 2 is latched off; CH2EN bit is reset and channel 2 is disabled until the CH2EN bit is programmed high by SPI command. |
3 | CH2LSILIMFL | R/W | 0 | Channel 2 low-side FET current limit fault response 0 = Channel 2 auto-restarts after the ILIM fault timer has expired. 1 = Channel 2 is latched off; CH2EN bit is reset and channel 2 is disabled until the CH2EN bit is programmed high by SPI command. |
2 | CH1TSFL | R/W | 0 | Channel 1 thermal shutdown fault response 0 = Channel 1 auto-restarts based on internal temperature hysteresis. 1 = Channel 1 is latched off; CH1EN bit is reset and channel 1 is disabled until the CH1EN bit is programmed high by SPI command. |
1 | CH1HSILIMFL | R/W | 0 | Channel 1 high side FET current limit fault response 0 = Channel 1 auto-restarts after the ILIM fault timer has expired. 1 = Channel 1 is latched off; CH1EN bit is reset and channel 1 is disabled until the CH1EN bit is programmed high by SPI command. |
0 | CH1LSILIMFL | R/W | 0 | Channel 1 low side FET current limit fault response 0 = Channel 1 auto-restarts after the ILIM fault timer has expired. 1 = Channel 1 is latched off; CH1EN bit is reset and channel 1 is disabled until the CH1EN bit is programmed high by SPI command. |