SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
The SYSCFG1 register is the first system configuration register and it contains bits associated with the enabling of channels and several device-related functions. Figure 7-22 shows SYSCFG1. Table 7-7 describes SYSCFG1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FPINRST | PWMPH | LHSW | CMWEN | CH2INTPWM | CH2EN | CH1INTPWM | CH1EN |
W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FPINRST | W | 0 | Reset open-drain fault output if there are no active faults in the system. Note that this bit is write-only. Any reads of this register return 0 in the FPINRST bit location. 0 = Do not care 1 = Reset open-drain fault output |
6 | PWMPH | R/W | 0 | PWM phase shift setting for internal PWM generator 0 = 180° phase shift between internally generated PWM signals 1 = 0° phase shift between internally generated PWM signals |
5 | LHSW | R/W | 0 | Software limp-home mode. The limp-home mode can be activated by writing to the register. The bit is also set high in case of communication failure. The bit has to be written to zero to return to normal operation. 0 = Normal Operation 1 = Operation in limp-home state |
4 | CMWEN | R/W | 1 | Communication watch dog timer 0 = Disable communication watch dog timer 1 = Enable communication watch dog timer |
3 | CH2INTPWM | R/W | 0 | This bit is used to enable internal PWM generator function for channel 2. 0 = LED current duty cycle of channel 2 controlled by the external signal connected to UDIM2 input 1 = LED current duty cycle of channel 2 controlled by the internal PWM generator (registers PWMDIV and CH2PWM). UDIM2 input must be above VUDIM2(UVLO). |
2 | CH2EN | R/W | 0 | CH2 enable. This bit controls the operation of channel 2. 0 = Disable LED channel 2 1 = Enable LED channel 2 |
1 | CH1INTPWM | R/W | 0 | This bit is used to enable internal PWM generator function for channel 1. 0 = LED current duty cycle of channel 1 controlled by external signal connected to UDIM1 input 1 = LED current duty cycle of channel 1 controlled by internal PWM generator (registers PWMDIV and CH1PWM). UDIM1 input must be above VUDIM1(UVLO). |
0 | CH1EN | R/W | 0 | CH1 enable. This bit controls the operation of channel 1. 0 = Disable LED channel 1 1 = Enable LED channel 1 |