No output delay
shown, COMP-to-RAMP offset not included.
There is no pulse
on OUTE during burst mode at start-up. Two falling edge PWM pulses are required
before enabling the synchronous rectifier outputs. Narrower pulse widths (less
than 50% duty cycle) may be observed in the 1st OUTD pulse of a burst. The user
must design the bootstrap capacitor charging circuit of the gate driver device
so that the first OUTC pulse is transmitted to the MOSFET gate in all cases.
Transformer based gate driver circuits are not affected. This behavior is
described in more detail in the
Gate Drive Outputs on the UCC28950
and UCC2895x During Burst Mode Operation
(SLAU787) application note.