SLUSDB2B August   2018  – October 2024 UCC28950 , UCC28951

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

UCC28950 UCC28951 PW Package, 24-Pin TSSOP (Top View) Figure 4-1 PW Package, 24-Pin TSSOP (Top View)
Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
ADEL 14 I Dead-time programming for the primary switches over CS voltage range, tABSET and tCDSET. See Section 6.3.6
ADELEF 13 I Delay-time programming between primary side and secondary side switches, tAFSET and tBESET. See Section 6.3.7
COMP 4 I/O Error amplifier output and input to the PWM comparator. See Section 6.3.3
CS 15 I Current sense for cycle-by-cycle overcurrent protection and adaptive delay functions. See Section 6.3.14
DCM 12 I DCM threshold setting. See Section 6.3.12
DELAB 6 I Dead-time delay programming between OUTA and OUTB. See Section 6.3.6
DELCD 7 I Dead-time delay programming between OUTC and OUTD. See Section 6.3.6
DELEF 8 I Delay-time programming between OUTA to OUTF, and OUTB to OUTE. See Section 6.3.7
EA+ 2 I Error amplifier noninverting input. See Section 6.3.3
EA– 3 I Error amplifier inverting input. See Section 6.3.3
GND 24 — Ground. All signals are referenced to this node.
OUTA 22 O 0.2A sink and source primary switching output.
OUTB 21 O
OUTC 20 O
OUTD 19 O
OUTE 18 O
OUTF 17 O
RSUM 11 I Slope compensation programming. Voltage mode or peak current mode setting. See Section 6.3.11
RT 10 I Oscillator frequency set. leader or follower mode setting. See Section 6.3.10
SS/EN 5 I Soft-start programming, device enable and hiccup mode protection circuit. See Section 6.3.4
SYNC 16 I/O Synchronization out from leader controller to input of follower controller. See Section 6.3.15
TMIN 9 I Minimum duty cycle programming in burst mode. See Section 6.3.9
VDD 23 I Bias supply input. See Section 6.3.17
VREF 1 O 5V, ±1.5%, 20mA reference voltage output. See Section 6.3.2