SLUSDC2C November   2018  – September 2019 UCC20225-Q1 , UCC20225A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Thermal Derating Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 PWM Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 Power-up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC20225-Q1 family
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing PWM Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Dead Time Setting Guidelines
        8. 9.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9.2.2.4 Estimate Gate Driver Power Loss

The total loss, PG, in the gate driver subsystem includes the power losses of the UCC20225-Q1 family (PGD) and the power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not included in PG and not discussed in this section.

PGD is the key power loss which determines the thermal safety-related limits of the UCC20225-Q1 family, and it can be estimated by calculating losses from several components.

The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and ambient temperature. Figure 4 shows the per output channel current consumption vs. operating frequency with no load. In this example, VVCCI = 5 V and VVDD = 12 V. The current on each power supply, with PWM switching from 0 V to 3.3 V at 200 kHz is measured to be IVCCI = 2 mA, and IVDDA = IVDDB = 1.5 mA. Therefore, the PGDQ can be calculated with

Equation 11. UCC20225-Q1 UCC20225A-Q1 sluscv6-equation-11.gif

The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be estimated with

Equation 12. UCC20225-Q1 UCC20225A-Q1 sluscv6-equation-12.gif

where

  • QG is the gate charge of the power transistor.

If a split rail is used to turn on and turn off, then VDD is the total difference between the positive rail to the negative rail.

So, for this example application:

Equation 13. UCC20225-Q1 UCC20225A-Q1 sluscv6-equation-13.gif

QG represents the total gate charge of the power transistor switching 400 V at 14 A, and is subject to change with different testing conditions. The UCC20225-Q1 family's gate driver loss on the output stage, PGDO, is part of PGSW. PGDO will be equal to PGSW if the external gate driver resistances and power transistor internal resistances are 0 Ω, and all the gate driver loss is dissipated inside the UCC20225-Q1 family. If there are external turn-on and turn-off resistance, the total loss will be distributed between the gate driver pull-up/down resistances, external gate resistances, and power transistor internal resistances. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

Equation 14. UCC20225-Q1 UCC20225A-Q1 sluscv6-equation-14.gif

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC20225-Q1 family's gate driver loss can be estimated with:

Equation 15. UCC20225-Q1 UCC20225A-Q1 sluscv6-equation-missing-1.gif

Case 2 - Nonlinear Pull-Up/Down Resistor:

Equation 16. UCC20225-Q1 UCC20225A-Q1 sluscv6-equation-missing-2.gif

where

  • VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off period. In cases where the output is saturated for some time, this can be simplified as a constant current source (4 A at turn-on and 6 A at turn-off) charging/discharging a load capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-down based on the above discussion.

Total gate driver loss dissipated in the gate driver UCC20225-Q1 family, PGD, is:

Equation 17. UCC20225-Q1 UCC20225A-Q1 sluscv6-equation-15.gif

which is equal to 127 mW in the design example.