SLUSDC7A March   2020  – November 2020 BQ25306

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Power Up
        1. 9.3.1.1 Power-On-Reset (POR)
        2. 9.3.1.2 REGN Regulator Power Up
        3. 9.3.1.3 Charger Power Up
        4. 9.3.1.4 Charger Enable and Disable by EN Pin
        5. 9.3.1.5 Device Unplugged from Input Source
      2. 9.3.2 Battery Charging Management
        1. 9.3.2.1 Battery Charging Profile
        2. 9.3.2.2 Precharge
        3. 9.3.2.3 Charging Termination
        4. 9.3.2.4 Battery Recharge
        5. 9.3.2.5 Charging Safety Timer
        6. 9.3.2.6 Thermistor Temperature Monitoring
      3. 9.3.3 Charging Status Indicator (STAT)
      4. 9.3.4 Protections
        1. 9.3.4.1 Voltage and Current Monitoring
          1. 9.3.4.1.1 Input Over-Voltage Protection
          2. 9.3.4.1.2 Input Voltage Dynamic Power Management (VINDPM)
          3. 9.3.4.1.3 Input Current Limit
          4. 9.3.4.1.4 Cycle-by-Cycle Current Limit
        2. 9.3.4.2 Thermal Regulation and Thermal Shutdown
        3. 9.3.4.3 Battery Protection
          1. 9.3.4.3.1 Battery Over-Voltage Protection (VBAT_OVP)
          2. 9.3.4.3.2 Battery Short Circuit Protection
        4. 9.3.4.4 ICHG Pin Open and Short Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Mode, HiZ Mode, Sleep Mode, Charge Mode, Termination Mode, and Fault Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Charge Voltage Settings
          2. 10.2.1.2.2 Charge Current Setting
          3. 10.2.1.2.3 Inductor Selection
          4. 10.2.1.2.4 Input Capacitor
          5. 10.2.1.2.5 Output Capacitor
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical Application with External Power Path
        1. 10.2.2.1 Design Requirements
      3. 10.2.3 Typical Application with MCU Programmable Charge Current
        1. 10.2.3.1 Design Requirements
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

7 Pin Configuration and Functions

GUID-783A3F5F-8FA7-4C93-B13C-311717D17142-low.gif Figure 7-1 RTE Package16-Pin WQFNTop View
Table 7-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
VBUS 1 P Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 2.2uF ceramic capacitor from VBUS to GND and place it as close as possible to IC.
PMID 16 P Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of high-side MOSFET (HSFET). Place ceramic 10μF on PMID to GND and place it as close as possible to IC.
SW 13,14 P Switching node. Connected to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047μF bootstrap capacitor from SW to BTST.
BTST 15 P High-side FET driver supply. Internally, the BTST is connected to the cathode of the internal boost-strap diode. Connect the 0.047μF bootstrap capacitor from SW to BTST.
GND 11,12 P Ground. Connected directly to thermal pad on the top layer. A single point connection is recommended between power ground and analog ground near the IC GND pins.
REGN 2 P Low-side FET driver positive supply output. Connect a 2.2μF ceramic capacitor from REGN to GND. The capacitor should be placed close to the IC.
BAT 10 AI Battery voltage sensing input. Connect this pin to the positive terminal of the battery pack and the node of inductor output terminal. 10-µF capacitor is recommended to connect to this pin.
TS 7 AI Battery temperature voltage input. Connect a negative temperature coefficient thermistor (NTC). Program temperature window with a resistor divider from REGN to TS and TS to GND. Charge suspends when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.
ICHG 4 AI Charge current program input. Connect a 1% resistor RICHG from this pin to ground to program the charge current as ICHG = KICHG / RICHG (KICHG = 40,000). No capacitor is allowed to connect at this pin. When ICHG pin is pulled to ground or left open, the charger stop switching and STAT pin starts blinking.
STAT 3 AO Charge status indication output. This pin is open drain output. Connect this pin to REGN via a current limiting resistor and LED. The STAT pin indicates charger status as:
  • Charge in progress: STAT pin is pulled LOW
  • Charge completed, charge disabled by EN: STAT pin is OPEN
  • Fault conditions: STAT pin blinks.
FB 9 AI Battery voltage feedback input. Connect this pin to resistor divider’s middle point to program battery charge voltage. When this pin is shorted to GND or open by fault, the converter stop switching and STAT pin blinks. The resistor divider consists of a resistor R1 from battery positive terminal to FB pin and a resistor R2 from FB pin to FB_GND. The recommended resistance value of R2 is 200kΩ or lower. The battery charge voltage is programmed as VBATREG = 1.1 (1 + R1/R2). The voltage regulation loop is internally compensated and a 470pF feedforward capacitor is recommended to connect from battery to FB pin.
FB_GND 8 AI Battery voltage feedback ground input. Connect the feedback resistor divider's low side resister to this pin. The input of this pin is in high impedance when adaptor is unplugged or the charger is disabled by EN pin.
POL 5 AI EN pin polority selection. Keep this pin floating for standalone charger.
EN 6 AI Device sisable input. With POL pin floating, the device is enabled with EN pin floating or pulled low, and the device is disabled if EN pin is pulled high. With POL pin grounded, the device is enabled with EN pin pulled high, and the device is disabled with EN pin pulled low or floating.
Thermal Pad 17 - Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane. Ground layer(s) are connected to thermal pad through vias under thermal pad.
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power