SLUSDC7A March   2020  – November 2020 BQ25306

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Power Up
        1. 9.3.1.1 Power-On-Reset (POR)
        2. 9.3.1.2 REGN Regulator Power Up
        3. 9.3.1.3 Charger Power Up
        4. 9.3.1.4 Charger Enable and Disable by EN Pin
        5. 9.3.1.5 Device Unplugged from Input Source
      2. 9.3.2 Battery Charging Management
        1. 9.3.2.1 Battery Charging Profile
        2. 9.3.2.2 Precharge
        3. 9.3.2.3 Charging Termination
        4. 9.3.2.4 Battery Recharge
        5. 9.3.2.5 Charging Safety Timer
        6. 9.3.2.6 Thermistor Temperature Monitoring
      3. 9.3.3 Charging Status Indicator (STAT)
      4. 9.3.4 Protections
        1. 9.3.4.1 Voltage and Current Monitoring
          1. 9.3.4.1.1 Input Over-Voltage Protection
          2. 9.3.4.1.2 Input Voltage Dynamic Power Management (VINDPM)
          3. 9.3.4.1.3 Input Current Limit
          4. 9.3.4.1.4 Cycle-by-Cycle Current Limit
        2. 9.3.4.2 Thermal Regulation and Thermal Shutdown
        3. 9.3.4.3 Battery Protection
          1. 9.3.4.3.1 Battery Over-Voltage Protection (VBAT_OVP)
          2. 9.3.4.3.2 Battery Short Circuit Protection
        4. 9.3.4.4 ICHG Pin Open and Short Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Mode, HiZ Mode, Sleep Mode, Charge Mode, Termination Mode, and Fault Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Charge Voltage Settings
          2. 10.2.1.2.2 Charge Current Setting
          3. 10.2.1.2.3 Inductor Selection
          4. 10.2.1.2.4 Input Capacitor
          5. 10.2.1.2.5 Output Capacitor
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical Application with External Power Path
        1. 10.2.2.1 Design Requirements
      3. 10.2.3 Typical Application with MCU Programmable Charge Current
        1. 10.2.3.1 Design Requirements
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

8.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OVP and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENT
IVBUS_REVS VBUS reverse current from BAT/SW to VBUS,  TJ = -40°C - 85°C VBAT = VSW = 4.5V, VBUS is shorted to GND, measure VBUS reverse current 0.07 3 µA
IVBUS_REVS VBUS reverse current from BAT/SW to VBUS TJ = -40°C - 85°C VBAT = VSW =  9.0V, VBUS is shorted to GND, measure VBUS reverse current 0.14 6 µA
IQ_VBUS_DIS VBUS leakage current in disable mode, TJ = -40°C - 85°C VBUS = 5V, VBAT = 4V, charger is disabled, /EN is pulled high 3.5 4.25 µA
IQ_VBUS_DIS VBUS leakage current in disable mode, TJ = -40°C - 85°C VBUS = 9V, VBAT = 4V, charger is disabled, /EN is pulled high 4.7 6 µA
IQ_BAT_HIZ BAT and SW pin leakage current in HiZ mode, TJ = -40°C - 65°C VBAT = VSW = 4.5V, VBUS floating 0.17 1.0 µA
IQ_BAT_DIS_9V BAT and SW pin leakage current in disable mode, TJ = -40°C - 65°C VBAT = VSW = 9V, ICHG connected to a 25kΩ resistor, VBUS floating 0.50 2 µA
VBUS POWER UP
VVBUS_OP VBUS operating range 4.1 17.0 V
VVBUS_UVLOZ VBUS power on reset VBUS rising 3.0 3.80 V
VVBUS_UVLOZ_HYS VBUS power on reset hysteresis VBUS falling 250 mV
VVBUS_LOWV A condition to turnon REGN VBUS rising, REGN turns on, VBAT = 3.2V 3.8 3.90 4.00 V
VVBUS_LOWV_HYS A condition to turnon REGN, hysteresis VBUS falling, REGN turns off, VBAT = 3.2V 300 mV
VSLEEP Enter sleep mode threshold VBUS falling, VBUS - VBAT, VVBUS_LOWV < VBAT < VBATREG 30 60 100 mV
VSLEEPZ Exit sleep mode threshold VBUS rising, VBUS - VBAT, VVBUS_LOWV < VBAT <  VBATREG 110 157 295 mV
VVBUS_OVP_RISE VBUS overvoltage rising threshold VBUS rising, converter stops switching 17.00 17.40 17.80 V
VVBUS_OVP_HYS VBUS overvoltage falling hysteresis VBUS falling, converter stops switching 750 mV
MOSFETS
RDSON_Q1 Top reverse blocking MOSFET on-resistance between VBUS and PMID (Q1) VREGN = 5V 40 65 mΩ
RDSON_Q2 High-side switching MOSFET on-resistance between PMID and SW (Q2) VREGN = 5V 50 82 mΩ
RDSON_Q3 Low-side switching MOSFET on-resistance between SW and GND (Q3) VREGN = 5V 45 72 mΩ
RDSON_FB_GND FB_GND MOSFET on-resistance between FB_GND and GND 38 Ω
BATTERY CHARGER
VBATREG_RANGE Charge voltage regulation range VVBUS = 12V, VBATREG is programmed by FB resistor divider 3.400 9.000 V
VFB_REF_VBATREG Battery feedback regulation voltage TJ = -40°C to +85°C 1094 1100 1104.5 mV
ICHG Charge current regulation ICHG set at 1.72A with RICHG=23.2kΩ 1.55 1.72 1.89 A
ICHG set at 1.0A with RICHG=40.2kΩ 0.90 1.00 1.10 A
ICHG set at 0.5A with RICHG=78.7kΩ 0.40 0.500 0.60 A
ITERM Termination current ICHG = 1.72A, 10% of ICHG, RICHG=23.2kΩ 138 172 206 mA
ITERM Termination current ICHG = 1.0A, 10% of ICHG, RICHG=40.2kΩ 70 100 130 mA
ITERM Termination current ICHG = 0.5A, ITERM =63mA RICHG=78.7kΩ 33 63 93 mA
IPRECHG Precharge current ICHG = 1.72A, 10% of ICHG, RICHG=23.2kΩ 115 172 225 mA
ICHG = 1.0A, 10% of ICHG, RICHG=40.2kΩ 50 100 150 mA
ICHG = 0.5A, 10% of ICHG, RICHG=78.7kΩ 28 63 98 mA
VBAT_SHORT_RISE VBAT short rising threshold Short to precharge 2.05 2.20 2.35 V
VBAT_SHORT_FALL VBAT short falling threshold Precharge to battery short 1.85 2.00 2.15 V
IBAT_SHORT Battery short current VBAT < VBAT_SHORT_FALL 25 35 46 mA
VFB_REF_LOWV_RISE VBATLOWV rising threshold Precharge to fast charge rising, as percentage of VFB_REF_VBATREG 68 70 72 %
VFB_REF_LOWV_FALL VBATLOWV falling threshold Fast charge to precharge falling, as percentage of VFB_REF_VBATREG 66 68 70 %
VFB_REF_RECHG Recharge threshold VFB falling, as percentage of VFB_REF_VBATREG 95.2 96.4 97.6 %
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_MIN Minimum input voltage regulation VBAT = 3.5V, measured at PMID pin 4.0 4.07 4.2 V
VINDPM Input voltage regulation VBAT = 4V, measured at PMID pin, VINDPM = 1.044*VBAT + 0.125V 4.15 4.30 4.41 V
VINDPM Input voltage regulation VBAT = 8V, measured at PMID pin, VINDPM = 1.044*VBAT + 0.125V 8.27 8.47 8.67 V
IINDPM_3A Input current regulation 3.00 3.35 3.70 A
BATTERY OVER-VOLTAGE PROTECTION
VFB_BAT_OVP_RISE Battery overvoltage rising threshold VBAT rising as percentage of VFB_REF_VBATREG 103 104 105 %
VFB_BAT_OVP_FALL Battery overvoltage falling threshold VBAT falling as percentage of VFB_REF_VBATREG 101 102 103 %
CONVERTER PROTECTION
VBTST_REFRESH Bootstrap refresh comparator threshold (VBTST - VSW) when LSFET refresh pulse is requested, VBUS = 5V 2.7 3 3.3 V
IHSFET_OCP HSFET cycle by cycle over current limit threshold 5.2 6.2 6.7 A
STAT INDICATION
ISTAT_SINK STAT pin sink current 6 mA
FBLINK STAT pin blink frequency 1 Hz
FBLINK_DUTY STAT pin blink duty cycle 50 %
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy 111 120 133 °C
TSHUT Thermal shutdown rising threshold Temperature increasing 150 °C
Thermal shutdown falling threshold Temperature decreasing 125 °C
BUCK MODE OPERATION
FSW PWM switching frequency SW node frequency 1.02 1.20 1.38 MHz
DMAX Maximum PWM Duty Cycle 97.0 %
REGN LDO
VREGN_UVLO REGN UVLO VVBUS rising 3.85 V
VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 0 to 16mA 4.2 5.0 V
VREGN REGN LDO output voltage VVBUS = 12V, IREGN = 16mA 4.50 5.40 V
ICHG SETTING
VICHG ICHG pin regulated voltage 993 998 1003 mV
RICHG_SHORT_FALL Maximum resistance to disable charge 1.0 kΩ
RICHG_OPEN_RISE Minimum resistance to disable charge 565 kΩ
RICHG_MAX Maximum programmable resistance at ICHG 250 kΩ
RICHG_MIN_SLE1 Minimum programmable resistance at ICHG 11.70 kΩ
RICHG_HIGH ICHG setting resistor threshold to clamp precharge and termination current to 63mA RICHG > RICHG_HIGH 60 65 70 kΩ
KICHG Charge current ratio ICHG set at 1.72A with RICHG = 23.2kΩ, ICHG = KICHG / RICHG 36000 40000 44000 AxΩ
KICHG Charge current ratio ICHG set at 1.0A with RICHG = 40.2kΩ, ICHG = KICHG / RICHG 36000 40280 44000 AxΩ
KICHG Charge current ratio ICHG set at 0.5A with RICHG = 78.7kΩ, ICHG = KICHG / RICHG 32000 40700 48000 AxΩ
COLD/HOT THERMISTOR COMPARATOR
VT1% TCOLD (0°C) threshold, charge suspended if thermistor temperature is below T1 VTS rising, as percentage to VREGN 72.68 73.5 74.35 %
VT1% VTS falling As Percentage to VREGN 70.68 71.5 72.33 %
VT3% THOT (45°C) threshold, charge suspended if thermistor temperature is above T_HOT VTS falling, as percentage to VREGN 46.35 47.25 48.15 %
VT3% VTS rising As percentage to VREGN 47.35 48.25 49.15 %
LOGIC I/O PIN CHARACTERESTICS (POL, EN)
VILO Input low threshold Falling 0.40 V
VIH Input high threshold Rising 1.3 V
IBIAS High-level leakage current at /EN pin /EN pin is pulled up to 1.8 V 1.0 µA