SLUSDF8E June   2019  – July 2024 BQ25618 , BQ25619

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On-Reset (POR)
      2. 7.3.2  Device Power Up From Battery Without Input Source
      3. 7.3.3  Power Up From Input Source
        1. 7.3.3.1 Power Up REGN LDO
        2. 7.3.3.2 Poor Source Qualification
        3. 7.3.3.3 Input Source Type Detection (IINDPM Threshold)
          1. 7.3.3.3.1 PSEL Pins Sets Input Current Limit
        4. 7.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 7.3.3.5 Power Up Converter in Buck Mode
        6. 7.3.3.6 HIZ Mode with Adapter Present
      4. 7.3.4  Boost Mode Operation From Battery
      5. 7.3.5  Power Path Management
        1. 7.3.5.1 Narrow VDC Architecture
        2. 7.3.5.2 Dynamic Power Management
        3. 7.3.5.3 Supplement Mode
      6. 7.3.6  Battery Charging Management
        1. 7.3.6.1 Autonomous Charging Cycle
        2. 7.3.6.2 Battery Charging Profile
        3. 7.3.6.3 Charging Termination
        4. 7.3.6.4 Thermistor Qualification
          1. 7.3.6.4.1 JEITA Guideline Compliance During Charging Mode
          2. 7.3.6.4.2 Boost Mode Thermistor Monitor During Battery Discharge Mode
        5. 7.3.6.5 Charging Safety Timer
      7. 7.3.7  Ship Mode and QON Pin
        1. 7.3.7.1 BATFET Disable (Enter Ship Mode)
        2. 7.3.7.2 BATFET Enable (Exit Ship Mode)
        3. 7.3.7.3 BATFET Full System Reset
      8. 7.3.8  Status Outputs (STAT, INT , PMID_GOOD)
        1. 7.3.8.1 Power Good Indicator (PG_STAT Bit)
        2. 7.3.8.2 Charging Status Indicator (STAT)
        3. 7.3.8.3 Interrupt to Host (INT)
        4. 7.3.8.4 PMID Voltage Indicator (PMID_GOOD)
      9. 7.3.9  Protections
        1. 7.3.9.1 Voltage and Current Monitoring in Buck Mode
          1. 7.3.9.1.1 Input Overvoltage Protection (ACOV)
          2. 7.3.9.1.2 System Overvoltage Protection (SYSOVP)
        2. 7.3.9.2 Voltage and Current Monitoring in Boost Mode
          1. 7.3.9.2.1 Boost Mode Overvoltage Protection
          2. 7.3.9.2.2 PMID Overcurrent Protection
        3. 7.3.9.3 Thermal Regulation and Thermal Shutdown
          1. 7.3.9.3.1 Thermal Protection in Buck Mode
          2. 7.3.9.3.2 Thermal Protection in Boost Mode
        4. 7.3.9.4 Battery Protection
          1. 7.3.9.4.1 Battery Overvoltage Protection (BATOVP)
          2. 7.3.9.4.2 Battery Overdischarge Protection
          3. 7.3.9.4.3 System Overcurrent Protection
      10. 7.3.10 Serial Interface
        1. 7.3.10.1 Data Validity
        2. 7.3.10.2 START and STOP Conditions
        3. 7.3.10.3 Byte Format
        4. 7.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.3.10.5 Slave Address and Data Direction Bit
        6. 7.3.10.6 Single Read and Write
        7. 7.3.10.7 Multi-Read and Multi-Write
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
    5. 7.5 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor and Resistor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

7.3.8.3 Interrupt to Host (INT)

In some applications, the host does not always monitor charger operation. The INT pulse notifies the host on device operation. The following events generate a 256-μs INT pulse.

  • Good input source detected:
    • VVBUS above battery (not in sleep)
    • VVBUS below VACOV threshold
    • VVBUS above VPOORSRC (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
  • Input adapter removed
  • USB/adapter source identified during Section 7.3.3.3.
  • Charge complete
  • Any FAULT event in REG09
  • VINDPM / IINDPM event detected (REG0A[1:0], maskable)
  • Top-off timer starts and expires

REG09[7:0] and REG0A[6:4] report charger operation faults and status change to the host. When a fault/status change occurs, the charger sends out an INT pulse and keeps the state in REG09[7:0]/REG0A[6:4] until the host reads the registers. Before the host reads REG09[7:0]/REG0A[6:4] and all the ones are cleared, the charger does not send any INT upon new fault/status change. To read the current status, the host has to read REG09/REG0A two times consecutively. The first read reports the pre-existing register status and the second read reports the current register status.