SLUSDL3A February 2019 – April 2019 BQ25883
PRODUCTION DATA.
REG16 is shown in Figure 56 and described in Table 32.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
Field | IBUS_ADC_DIS | ICHG_ADC_DIS | VBUS_ADC_DIS | VBAT_ADC_DIS | VSYS_ADC_DIS | TS_ADC_DIS | Reserved | TDIE_ADC_DIS |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | IBUS_ADC_DIS | R/W | Yes | No | 0 – Enable conversion
1 – Disable conversion |
|
6 | ICHG_ADC_DIS | R/W | Yes | No | 0 – Enable conversion
1 – Disable conversion |
|
5 | VBUS_ADC_DIS | R/W | Yes | No | 0 – Enable conversion
1 – Disable conversion |
|
4 | VBAT_ADC_DIS | R/W | Yes | No | 0 – Enable conversion
1 – Disable conversion |
|
3 | VSYS_ADC_DIS | R/W | Yes | No | 0 – Enable conversion
1 – Disable conversion |
|
2 | TS_ADC_DIS | R/W | Yes | No | 0 – Enable conversion
1 – Disable conversion |
|
1 | RESERVED | R | Yes | No | Reserved bit always reads 1h | |
0 | TDIE_ADC_DIS | R/W | Yes | No | 0 – Enable conversion
1 – Disable conversion |