SLUSDL3A February 2019 – April 2019 BQ25883
PRODUCTION DATA.
REG01 is shown in Figure 35 and described in Table 11.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 0h | 1h | 1Eh | |||||
Field | EN_HIZ | EN_ILIM | ICHG[5:0] |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | EN_HIZ | R/W | Yes | Yes | Enable HIZ Mode:
0 – Disable (default) 1 – Enable |
|
6 | EN_ILIM | R/W | Yes | Yes | Enable ILIM Pin Function:
0 – Disable 1 – Enable (default) |
|
5 | ICHG[5] | R/W | Yes | Yes | 1600 mA | Fast Charge Current Limit
Offset: 100 mA Range: 100mA – 2200mA Default 1500 mA Note: ICHG > 2.2A (2Ch) clamped to 2.2A. ICHG < 100mA (01h) clamped at 100mA |
4 | ICHG[4] | R/W | Yes | Yes | 800 mA | |
3 | ICHG[3] | R/W | Yes | Yes | 400 mA | |
2 | ICHG[2] | R/W | Yes | Yes | 200 mA | |
1 | ICHG[1] | R/W | Yes | Yes | 100 mA | |
0 | ICHG[0] | R/W | Yes | Yes | 50 mA |