SLUSDQ4 April 2019 BQ79606A-Q1
PRODUCTION DATA.
To setup continuous ADC conversion, the host enables the cells using the CELL_ADC_CTRL register as with the single conversion case. Additionally, the host must set the CELL_ADC_CONF2[CELL_CONT] bit. The conversion interval between cell ADC conversions is programmed using the CELL_ADC_CONF2[CELL_INT] bit. After these registers are updated, the host must send a second write to set the CONTROL2[CELL_ADC_GO] bit.
Once the first conversion is complete, the ADC waits the programmed interval time (set by CELL_ADC_CONF2[CELL_INT]) and starts the next conversion.
Once all of the cell conversions are complete for the first interval, the DEV_STAT[DRDY_CELL] is set. The DEV_STAT[DRDY_CELL] bit remains set after the first conversion during continuous conversions. The flag is cleared only when a new ADC conversion is initiated by writing the CONTROL2[CELL_ADC_GO] bit. Additionally, a 14-bit counter (CONV_CNT*) keeps track of the number of conversions done during the continuous conversion mode. The counter is incremented with every conversion. During continuous conversions, the last valid conversion results are always available in the results registers after the H byte register is read. To stop continuous conversions, the host must clear the ADC_CONF2[CELL_CONT] bit and then write the CONTROL2[CELL_ADC_GO] bit. This will begin one additional conversion, but the continuous conversions are discontinued.
During continuous conversions, any changes to the CELL_ADC_CONF* and CELL_ADC_CTRL registers are ignored. To make changes during continuous conversions, the host must stop ADC conversions by clearing the CELL_ADC_CONF2[CELL_CONT] bit and then writing the CONTROL2[CELL_ADC_GO] bit to stop the continuous conversions, update the CELL_ADC_CONF*, and CELL_ADC_CTRL registers, and then set the CONTROL2[CELL_ADC_GO] bit to restart continuous conversions. For best results when using the single pole lowpass digital filter, the cell conversions must be set to continuous conversions with the minimum interval setting.