SLUSDQ4 April   2019 BQ79606A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified System Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
        1. 8.3.1.1 AVDD LDO
        2. 8.3.1.2 VLDO LDO
        3. 8.3.1.3 DVDD LDO
        4. 8.3.1.4 TSREF
        5. 8.3.1.5 Internal Supply Rails
        6. 8.3.1.6 CVDD and VIO Supplies
        7. 8.3.1.7 Startup
      2. 8.3.2 Precision References
      3. 8.3.3 Analog Front End
        1. 8.3.3.1 VC Current Sinks and Sources
      4. 8.3.4 Delta-Sigma (ΔΣ) Converters
        1. 8.3.4.1 ADC Architecture
          1. 8.3.4.1.1 Internal Input Filter
          2. 8.3.4.1.2 Modulator
          3. 8.3.4.1.3 SINC3 Digital Filter (CIC)
            1. 8.3.4.1.3.1 Example Frequency Response of a Delta-Sigma Converter
          4. 8.3.4.1.4 Single Pole Digital Filter
        2. 8.3.4.2 CELL ADC
          1. 8.3.4.2.1 Continuous CELL ADC Conversions
          2. 8.3.4.2.2 On-Demand CELL ADC Conversion (Single Conversion)
        3. 8.3.4.3 DIE Temperature ADC Measurement
        4. 8.3.4.4 AUX ADC
          1. 8.3.4.4.1 On-Demand AUX ADC Conversion (Single Conversion)
          2. 8.3.4.4.2 AUX CELL Voltage
          3. 8.3.4.4.3 AUX GPIO Input Measurement
          4. 8.3.4.4.4 AUX BAT Measurement
          5. 8.3.4.4.5 Power Rail, DAC, References, and 0V Measurements
          6. 8.3.4.4.6 VWARN PTAT measurement
      5. 8.3.5 Cell Balancing
        1. 8.3.5.1 Cell Balancing Setup and Sequencing
          1. 8.3.5.1.1 Cell Voltage Monitoring Setup
          2. 8.3.5.1.2 Timer Setup and Configuration
          3. 8.3.5.1.3 Cell Balance Sequencing
          4. 8.3.5.1.4 Manual Cell Balance Switch Enable
        2. 8.3.5.2 Cell Balance Diagnostics
          1. 8.3.5.2.1 Cell Balance Switch Comparators
          2. 8.3.5.2.2 CB Current Sinks and Sources
      6. 8.3.6 Integrated Hardware Protector
        1. 8.3.6.1 Cell Voltage Window Comparators
        2. 8.3.6.2 Cell Over/Under-Temperature Comparators
        3. 8.3.6.3 CB_DONE, OVUV, and OTUT Built-In Self Test (BIST)
        4. 8.3.6.4 Single Comparator Mode
          1. 8.3.6.4.1 OTUT DAC Measurmenent
          2. 8.3.6.4.2 OVUV DAC Measurment
      7. 8.3.7 Thermal Shutdown and Warning
      8. 8.3.8 Oscillator Watchdogs
      9. 8.3.9 Digital Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 POR (Power On Reset)
        2. 8.4.1.2 SHUTDOWN Mode
        3. 8.4.1.3 SLEEP Mode
        4. 8.4.1.4 ACTIVE Mode
    5. 8.5 Communication, Programming, GPIO, and Safety
      1. 8.5.1 Communication Interfaces and Programming
        1. 8.5.1.1 UART Communication Physical Layer
          1. 8.5.1.1.1 UART Interface
            1. 8.5.1.1.1.1 UART Transmitter
            2. 8.5.1.1.1.2 UART Receiver
            3. 8.5.1.1.1.3 UART Baud Rate Selection
            4. 8.5.1.1.1.4 Communication Clear (Break) Detection
            5. 8.5.1.1.1.5 Communication Reset Detection
        2. 8.5.1.2 Command and Response Protocol Layer
          1. 8.5.1.2.1 Transaction Frame Description
            1. 8.5.1.2.1.1 Frame Initialization Byte
            2. 8.5.1.2.1.2 Device Address Byte
            3. 8.5.1.2.1.3 Register Address Bytes
            4. 8.5.1.2.1.4 Data Byte(s)
            5. 8.5.1.2.1.5 CRC Bytes
              1. 8.5.1.2.1.5.1 Calculating Frame CRC Value
              2. 8.5.1.2.1.5.2 Verifying Frame CRC
              3. 8.5.1.2.1.5.3 Communication CRC Diagnostics
          2. 8.5.1.2.2 Transaction Frame Examples
            1. 8.5.1.2.2.1 Single Device Read Command Frame
            2. 8.5.1.2.2.2 Single Device Write Command Frame
            3. 8.5.1.2.2.3 Stack Read Command Frame
            4. 8.5.1.2.2.4 Stack Write Command Frame
            5. 8.5.1.2.2.5 Broadcast Read Command Frame
            6. 8.5.1.2.2.6 Broadcast Write Command Frame
            7. 8.5.1.2.2.7 Broadcast Write Reverse Direction
            8. 8.5.1.2.2.8 Response Frame
        3. 8.5.1.3 Daisy Chain Communication
          1. 8.5.1.3.1 Daisy Chain Transmitter and Receiver Functionality
          2. 8.5.1.3.2 Daisy Chain Protocol Description
          3. 8.5.1.3.3 Ring Architecture
          4. 8.5.1.3.4 Communication Diagnostics
            1. 8.5.1.3.4.1 Byte Errors
            2. 8.5.1.3.4.2 Frame Counters
        4. 8.5.1.4 Wakeup and Shutdown
          1. 8.5.1.4.1 Base Device Wakeup and Hardware Shutdown
          2. 8.5.1.4.2 Stack Device Wakeup and Hardware Shutdown
        5. 8.5.1.5 Fault Handling
          1. 8.5.1.5.1 Fault Status
            1. 8.5.1.5.1.1 Fault Reset
          2. 8.5.1.5.2 Fault Masking
          3. 8.5.1.5.3 Fault Signaling
            1. 8.5.1.5.3.1 NFAULT Output (Base Device)
            2. 8.5.1.5.3.2 Daisy-Chain FAULT* Interface (Stack Devices)
              1. 8.5.1.5.3.2.1 FAULT* Interface Tones
        6. 8.5.1.6 Communication Timeouts
          1. 8.5.1.6.1 Short Communications Timeout Fault
          2. 8.5.1.6.2 Long Communications Timeout Fault
        7. 8.5.1.7 Non-Volatile Memory
          1. 8.5.1.7.1 OTP Page Status
          2. 8.5.1.7.2 Programming NVM
            1. 8.5.1.7.2.1 CUST OTP Programming
          3. 8.5.1.7.3 NVM CRC Testing
          4. 8.5.1.7.4 CRC Faults
          5. 8.5.1.7.5 Computing Customer CRC
        8. 8.5.1.8 Error Check and Correct (ECC) OTP
          1. 8.5.1.8.1 ECC Diagnostic Test
      2. 8.5.2 General Purpose IOs and SPI
        1. 8.5.2.1 GPIO ADC Measurements
        2. 8.5.2.2 SPI Master Interface
          1. 8.5.2.2.1 CPOL=0, CPHA=0
          2. 8.5.2.2.2 CPOL=0, CPHA=1
          3. 8.5.2.2.3 CPOL=1, CPHA=0
          4. 8.5.2.2.4 CPOL=1, CPHA=1
          5. 8.5.2.2.5 SPI Master Protocol
            1. 8.5.2.2.5.1 SPI Write Examples
            2. 8.5.2.2.5.2 SPI Read Examples
        3. 8.5.2.3 SPI Loopback Function
      3. 8.5.3 Safety Mechanisms
    6. 8.6 Register Maps
      1. 8.6.1 Customer Registers
        1. 8.6.1.1   Register Summary Table
        2. 8.6.1.2   Register: DEVADD_OTP
        3. 8.6.1.3   Register: CONFIG
        4. 8.6.1.4   Register: GPIO_FLT_MSK
        5. 8.6.1.5   Register: UV_FLT_MSK
        6. 8.6.1.6   Register: OV_FLT_MSK
        7. 8.6.1.7   Register: UT_FLT_MSK
        8. 8.6.1.8   Register: OT_FLT_MSK
        9. 8.6.1.9   Register: TONE_FLT_MSK
        10. 8.6.1.10  Register: COMM_UART_FLT_MSK
        11. 8.6.1.11  Register: COMM_UART_RC_FLT_MSK
        12. 8.6.1.12  Register: COMM_UART_RR_FLT_MSK
        13. 8.6.1.13  Register: COMM_UART_TR_FLT_MSK
        14. 8.6.1.14  Register: COMM_COMH_FLT_MSK
        15. 8.6.1.15  Register: COMM_COMH_RC_FLT_MSK
        16. 8.6.1.16  Register: COMM_COMH_RR_FLT_MSK
        17. 8.6.1.17  Register: COMM_COMH_TR_FLT_MSK
        18. 8.6.1.18  Register: COMM_COML_FLT_MSK
        19. 8.6.1.19  Register: COMM_COML_RC_FLT_MSK
        20. 8.6.1.20  Register: COMM_COML_RR_FLT_MSK
        21. 8.6.1.21  Register: COMM_COML_TR_FLT_MSK
        22. 8.6.1.22  Register: OTP_FLT_MSK
        23. 8.6.1.23  Register: RAIL_FLT_MSK
        24. 8.6.1.24  Register: SYS_FLT1_FLT_MSK
        25. 8.6.1.25  Register: SYS_FLT2_FLT_MSK
        26. 8.6.1.26  Register: SYS_FLT3_FLT_MSK
        27. 8.6.1.27  Register: OVUV_BIST_FLT_MSK
        28. 8.6.1.28  Register: OTUT_BIST_FLT_MSK
        29. 8.6.1.29  Register: SPARE_01
        30. 8.6.1.30  Register: SPARE_02
        31. 8.6.1.31  Register: SPARE_03
        32. 8.6.1.32  Register: SPARE_04
        33. 8.6.1.33  Register: SPARE_05
        34. 8.6.1.34  Register: COMM_CTRL
        35. 8.6.1.35  Register: DAISY_CHAIN_CTRL
        36. 8.6.1.36  Register: TX_HOLD_OFF
        37. 8.6.1.37  Register: COMM_TO
        38. 8.6.1.38  Register: CELL_ADC_CONF1
        39. 8.6.1.39  Register: CELL_ADC_CONF2
        40. 8.6.1.40  Register: AUX_ADC_CONF
        41. 8.6.1.41  Register: ADC_DELAY
        42. 8.6.1.42  Register: GPIO_ADC_CONF
        43. 8.6.1.43  Register: OVUV_CTRL
        44. 8.6.1.44  Register: UV_THRESH
        45. 8.6.1.45  Register: OV_THRESH
        46. 8.6.1.46  Register: OTUT_CTRL
        47. 8.6.1.47  Register: OTUT_THRESH
        48. 8.6.1.48  Register: COMP_DG
        49. 8.6.1.49  Register: GPIO1_CONF
        50. 8.6.1.50  Register: GPIO2_CONF
        51. 8.6.1.51  Register: GPIO3_CONF
        52. 8.6.1.52  Register: GPIO4_CONF
        53. 8.6.1.53  Register: GPIO5_CONF
        54. 8.6.1.54  Register: GPIO6_CONF
        55. 8.6.1.55  Register: CELL1_GAIN
        56. 8.6.1.56  Register: CELL2_GAIN
        57. 8.6.1.57  Register: CELL3_GAIN
        58. 8.6.1.58  Register: CELL4_GAIN
        59. 8.6.1.59  Register: CELL5_GAIN
        60. 8.6.1.60  Register: CELL6_GAIN
        61. 8.6.1.61  Register: CELL1_OFF
        62. 8.6.1.62  Register: CELL2_OFF
        63. 8.6.1.63  Register: CELL3_OFF
        64. 8.6.1.64  Register: CELL4_OFF
        65. 8.6.1.65  Register: CELL5_OFF
        66. 8.6.1.66  Register: CELL6_OFF
        67. 8.6.1.67  Register: GPIO1_GAIN
        68. 8.6.1.68  Register: GPIO2_GAIN
        69. 8.6.1.69  Register: GPIO3_GAIN
        70. 8.6.1.70  Register: GPIO4_GAIN
        71. 8.6.1.71  Register: GPIO5_GAIN
        72. 8.6.1.72  Register: GPIO6_GAIN
        73. 8.6.1.73  Register: GPIO1_OFF
        74. 8.6.1.74  Register: GPIO2_OFF
        75. 8.6.1.75  Register: GPIO3_OFF
        76. 8.6.1.76  Register: GPIO4_OFF
        77. 8.6.1.77  Register: GPIO5_OFF
        78. 8.6.1.78  Register: GPIO6_OFF
        79. 8.6.1.79  Register: GPAUXCELL_GAIN
        80. 8.6.1.80  Register: GPAUXCELL_OFF
        81. 8.6.1.81  Register: GPAUX_GAIN
        82. 8.6.1.82  Register: GPAUX_OFF
        83. 8.6.1.83  Register: VC1COEFF1
        84. 8.6.1.84  Register: VC1COEFF2
        85. 8.6.1.85  Register: VC1COEFF3
        86. 8.6.1.86  Register: VC1COEFF4
        87. 8.6.1.87  Register: VC1COEFF5
        88. 8.6.1.88  Register: VC1COEFF6
        89. 8.6.1.89  Register: VC1COEFF7
        90. 8.6.1.90  Register: VC1COEFF8
        91. 8.6.1.91  Register: VC1COEFF9
        92. 8.6.1.92  Register: VC1COEFF10
        93. 8.6.1.93  Register: VC1COEFF11
        94. 8.6.1.94  Register: VC1COEFF12
        95. 8.6.1.95  Register: VC1COEFF13
        96. 8.6.1.96  Register: VC1COEFF14
        97. 8.6.1.97  Register: VC2COEFF1
        98. 8.6.1.98  Register: VC2COEFF2
        99. 8.6.1.99  Register: VC2COEFF3
        100. 8.6.1.100 Register: VC2COEFF4
        101. 8.6.1.101 Register: VC2COEFF5
        102. 8.6.1.102 Register: VC2COEFF6
        103. 8.6.1.103 Register: VC2COEFF7
        104. 8.6.1.104 Register: VC2COEFF8
        105. 8.6.1.105 Register: VC2COEFF9
        106. 8.6.1.106 Register: VC2COEFF10
        107. 8.6.1.107 Register: VC2COEFF11
        108. 8.6.1.108 Register: VC2COEFF12
        109. 8.6.1.109 Register: VC2COEFF13
        110. 8.6.1.110 Register: VC2COEFF14
        111. 8.6.1.111 Register: VC3COEFF1
        112. 8.6.1.112 Register: VC3COEFF2
        113. 8.6.1.113 Register: VC3COEFF3
        114. 8.6.1.114 Register: VC3COEFF4
        115. 8.6.1.115 Register: VC3COEFF5
        116. 8.6.1.116 Register: VC3COEFF6
        117. 8.6.1.117 Register: VC3COEFF7
        118. 8.6.1.118 Register: VC3COEFF8
        119. 8.6.1.119 Register: VC3COEFF9
        120. 8.6.1.120 Register: VC3COEFF10
        121. 8.6.1.121 Register: VC3COEFF11
        122. 8.6.1.122 Register: VC3COEFF12
        123. 8.6.1.123 Register: VC3COEFF13
        124. 8.6.1.124 Register: VC3COEFF14
        125. 8.6.1.125 Register: VC4COEFF1
        126. 8.6.1.126 Register: VC4COEFF2
        127. 8.6.1.127 Register: VC4COEFF3
        128. 8.6.1.128 Register: VC4COEFF4
        129. 8.6.1.129 Register: VC4COEFF5
        130. 8.6.1.130 Register: VC4COEFF6
        131. 8.6.1.131 Register: VC4COEFF7
        132. 8.6.1.132 Register: VC4COEFF8
        133. 8.6.1.133 Register: VC4COEFF9
        134. 8.6.1.134 Register: VC4COEFF10
        135. 8.6.1.135 Register: VC4COEFF11
        136. 8.6.1.136 Register: VC4COEFF12
        137. 8.6.1.137 Register: VC4COEFF13
        138. 8.6.1.138 Register: VC4COEFF14
        139. 8.6.1.139 Register: VC5COEFF1
        140. 8.6.1.140 Register: VC5COEFF2
        141. 8.6.1.141 Register: VC5COEFF3
        142. 8.6.1.142 Register: VC5COEFF4
        143. 8.6.1.143 Register: VC5COEFF5
        144. 8.6.1.144 Register: VC5COEFF6
        145. 8.6.1.145 Register: VC5COEFF7
        146. 8.6.1.146 Register: VC5COEFF8
        147. 8.6.1.147 Register: VC5COEFF9
        148. 8.6.1.148 Register: VC5COEFF10
        149. 8.6.1.149 Register: VC5COEFF11
        150. 8.6.1.150 Register: VC5COEFF12
        151. 8.6.1.151 Register: VC5COEFF13
        152. 8.6.1.152 Register: VC5COEFF14
        153. 8.6.1.153 Register: VC6COEFF1
        154. 8.6.1.154 Register: VC6COEFF2
        155. 8.6.1.155 Register: VC6COEFF3
        156. 8.6.1.156 Register: VC6COEFF4
        157. 8.6.1.157 Register: VC6COEFF5
        158. 8.6.1.158 Register: VC6COEFF6
        159. 8.6.1.159 Register: VC6COEFF7
        160. 8.6.1.160 Register: VC6COEFF8
        161. 8.6.1.161 Register: VC6COEFF9
        162. 8.6.1.162 Register: VC6COEFF10
        163. 8.6.1.163 Register: VC6COEFF11
        164. 8.6.1.164 Register: VC6COEFF12
        165. 8.6.1.165 Register: VC6COEFF13
        166. 8.6.1.166 Register: VC6COEFF14
        167. 8.6.1.167 Register: VAUXCOEFF1
        168. 8.6.1.168 Register: VAUXCOEFF2
        169. 8.6.1.169 Register: VAUXCOEFF3
        170. 8.6.1.170 Register: VAUXCOEFF4
        171. 8.6.1.171 Register: VAUXCOEFF5
        172. 8.6.1.172 Register: VAUXCOEFF6
        173. 8.6.1.173 Register: VAUXCOEFF7
        174. 8.6.1.174 Register: VAUXCOEFF8
        175. 8.6.1.175 Register: VAUXCOEFF9
        176. 8.6.1.176 Register: VAUXCOEFF10
        177. 8.6.1.177 Register: VAUXCOEFF11
        178. 8.6.1.178 Register: VAUXCOEFF12
        179. 8.6.1.179 Register: VAUXCOEFF13
        180. 8.6.1.180 Register: VAUXCOEFF14
        181. 8.6.1.181 Register: VAUXCELLCOEFF1
        182. 8.6.1.182 Register: VAUXCELLCOEFF2
        183. 8.6.1.183 Register: VAUXCELLCOEFF3
        184. 8.6.1.184 Register: VAUXCELLCOEFF4
        185. 8.6.1.185 Register: VAUXCELLCOEFF5
        186. 8.6.1.186 Register: VAUXCELLCOEFF6
        187. 8.6.1.187 Register: VAUXCELLCOEFF7
        188. 8.6.1.188 Register: VAUXCELLCOEFF8
        189. 8.6.1.189 Register: VAUXCELLCOEFF9
        190. 8.6.1.190 Register: VAUXCELLCOEFF10
        191. 8.6.1.191 Register: VAUXCELLCOEFF11
        192. 8.6.1.192 Register: VAUXCELLCOEFF12
        193. 8.6.1.193 Register: VAUXCELLCOEFF13
        194. 8.6.1.194 Register: VAUXCELLCOEFF14
        195. 8.6.1.195 Register: SPARE_6
        196. 8.6.1.196 Register: CUST_MISC1
        197. 8.6.1.197 Register: CUST_MISC2
        198. 8.6.1.198 Register: CUST_MISC3
        199. 8.6.1.199 Register: CUST_MISC4
        200. 8.6.1.200 Register: CUST_CRCH
        201. 8.6.1.201 Register: CUST_CRCL
        202. 8.6.1.202 Register: OTP_PROG_UNLOCK1A
        203. 8.6.1.203 Register: OTP_PROG_UNLOCK1B
        204. 8.6.1.204 Register: OTP_PROG_UNLOCK1C
        205. 8.6.1.205 Register: OTP_PROG_UNLOCK1D
        206. 8.6.1.206 Register: DEVADD_USR
        207. 8.6.1.207 Register: CONTROL1
        208. 8.6.1.208 Register: CONTROL2
        209. 8.6.1.209 Register: OTP_PROG_CTRL
        210. 8.6.1.210 Register: GPIO_OUT
        211. 8.6.1.211 Register: CELL_ADC_CTRL
        212. 8.6.1.212 Register: AUX_ADC_CTRL1
        213. 8.6.1.213 Register: AUX_ADC_CTRL2
        214. 8.6.1.214 Register: AUX_ADC_CTRL3
        215. 8.6.1.215 Register: CB_CONFIG
        216. 8.6.1.216 Register: CB_CELL1_CTRL
        217. 8.6.1.217 Register: CB_CELL2_CTRL
        218. 8.6.1.218 Register: CB_CELL3_CTRL
        219. 8.6.1.219 Register: CB_CELL4_CTRL
        220. 8.6.1.220 Register: CB_CELL5_CTRL
        221. 8.6.1.221 Register: CB_CELL6_CTRL
        222. 8.6.1.222 Register: CB_DONE_THRESH
        223. 8.6.1.223 Register: CB_SW_EN
        224. 8.6.1.224 Register: DIAG_CTRL1
        225. 8.6.1.225 Register: DIAG_CTRL2
        226. 8.6.1.226 Register: DIAG_CTRL3
        227. 8.6.1.227 Register: DIAG_CTRL4
        228. 8.6.1.228 Register: VC_CS_CTRL
        229. 8.6.1.229 Register: CB_CS_CTRL
        230. 8.6.1.230 Register: CBVC_COMP_CTRL
        231. 8.6.1.231 Register: ECC_TEST
        232. 8.6.1.232 Register: ECC_DATAIN0
        233. 8.6.1.233 Register: ECC_DATAIN1
        234. 8.6.1.234 Register: ECC_DATAIN2
        235. 8.6.1.235 Register: ECC_DATAIN3
        236. 8.6.1.236 Register: ECC_DATAIN4
        237. 8.6.1.237 Register: ECC_DATAIN5
        238. 8.6.1.238 Register: ECC_DATAIN6
        239. 8.6.1.239 Register: ECC_DATAIN7
        240. 8.6.1.240 Register: ECC_DATAIN8
        241. 8.6.1.241 Register: GPIO_FLT_RST
        242. 8.6.1.242 Register: UV_FLT_RST
        243. 8.6.1.243 Register: OV_FLT_RST
        244. 8.6.1.244 Register: UT_FLT_RST
        245. 8.6.1.245 Register: OT_FLT_RST
        246. 8.6.1.246 Register: TONE_FLT_RST
        247. 8.6.1.247 Register: COMM_UART_FLT_RST
        248. 8.6.1.248 Register: COMM_UART_RC_FLT_RST
        249. 8.6.1.249 Register: COMM_UART_RR_FLT_RST
        250. 8.6.1.250 Register: COMM_UART_TR_FLT_RST
        251. 8.6.1.251 Register: COMM_COMH_FLT_RST
        252. 8.6.1.252 Register: COMM_COMH_RC_FLT_RST
        253. 8.6.1.253 Register: COMM_COMH_RR_FLT_RST
        254. 8.6.1.254 Register: COMM_COMH_TR_FLT_RST
        255. 8.6.1.255 Register: COMM_COML_FLT_RST
        256. 8.6.1.256 Register: COMM_COML_RC_FLT_RST
        257. 8.6.1.257 Register: COMM_COML_RR_FLT_RST
        258. 8.6.1.258 Register: COMM_COML_TR_FLT_RST
        259. 8.6.1.259 Register: OTP_FLT_RST
        260. 8.6.1.260 Register: RAIL_FLT_RST
        261. 8.6.1.261 Register: SYS_FLT1_RST
        262. 8.6.1.262 Register: SYS_FLT2_RST
        263. 8.6.1.263 Register: SYS_FLT3_RST
        264. 8.6.1.264 Register: OVUV_BIST_FLT_RST
        265. 8.6.1.265 Register: OTUT_BIST_FLT_RST
        266. 8.6.1.266 Register: OTP_PROG_UNLOCK2A
        267. 8.6.1.267 Register: OTP_PROG_UNLOCK2B
        268. 8.6.1.268 Register: OTP_PROG_UNLOCK2C
        269. 8.6.1.269 Register: OTP_PROG_UNLOCK2D
        270. 8.6.1.270 Register: SPI_CFG
        271. 8.6.1.271 Register: SPI_TX
        272. 8.6.1.272 Register: SPI_EXE
        273. 8.6.1.273 Register: PARTID
        274. 8.6.1.274 Register: SYS_FAULT1
        275. 8.6.1.275 Register: SYS_FAULT2
        276. 8.6.1.276 Register: SYS_FAULT3
        277. 8.6.1.277 Register: DEV_STAT
        278. 8.6.1.278 Register: LOOP_STAT
        279. 8.6.1.279 Register: FAULT_SUMMARY
        280. 8.6.1.280 Register: VCELL1_HF
        281. 8.6.1.281 Register: VCELL1_LF
        282. 8.6.1.282 Register: VCELL2_HF
        283. 8.6.1.283 Register: VCELL2_LF
        284. 8.6.1.284 Register: VCELL3_HF
        285. 8.6.1.285 Register: VCELL3_LF
        286. 8.6.1.286 Register: VCELL4_HF
        287. 8.6.1.287 Register: VCELL4_LF
        288. 8.6.1.288 Register: VCELL5_HF
        289. 8.6.1.289 Register: VCELL5_LF
        290. 8.6.1.290 Register: VCELL6_HF
        291. 8.6.1.291 Register: VCELL6_LF
        292. 8.6.1.292 Register: CONV_CNTH
        293. 8.6.1.293 Register: CONV_CNTL
        294. 8.6.1.294 Register: VCELL1H
        295. 8.6.1.295 Register: VCELL1L
        296. 8.6.1.296 Register: VCELL2H
        297. 8.6.1.297 Register: VCELL2L
        298. 8.6.1.298 Register: VCELL3H
        299. 8.6.1.299 Register: VCELL3L
        300. 8.6.1.300 Register: VCELL4H
        301. 8.6.1.301 Register: VCELL4L
        302. 8.6.1.302 Register: VCELL5H
        303. 8.6.1.303 Register: VCELL5L
        304. 8.6.1.304 Register: VCELL6H
        305. 8.6.1.305 Register: VCELL6L
        306. 8.6.1.306 Register: VCELL_FACTCORRH
        307. 8.6.1.307 Register: VCELL_FACTCORRL
        308. 8.6.1.308 Register: AUX_CELLH
        309. 8.6.1.309 Register: AUX_CELLL
        310. 8.6.1.310 Register: AUX_BATH
        311. 8.6.1.311 Register: AUX_BATL
        312. 8.6.1.312 Register: AUX_REF2H
        313. 8.6.1.313 Register: AUX_REF2L
        314. 8.6.1.314 Register: AUX_ZEROH
        315. 8.6.1.315 Register: AUX_ZEROL
        316. 8.6.1.316 Register: AUX_AVDDH
        317. 8.6.1.317 Register: AUX_AVDDL
        318. 8.6.1.318 Register: AUX_GPIO1H
        319. 8.6.1.319 Register: AUX_GPIO1L
        320. 8.6.1.320 Register: AUX_GPIO2H
        321. 8.6.1.321 Register: AUX_GPIO2L
        322. 8.6.1.322 Register: AUX_GPIO3H
        323. 8.6.1.323 Register: AUX_GPIO3L
        324. 8.6.1.324 Register: AUX_GPIO4H
        325. 8.6.1.325 Register: AUX_GPIO4L
        326. 8.6.1.326 Register: AUX_GPIO5H
        327. 8.6.1.327 Register: AUX_GPIO5L
        328. 8.6.1.328 Register: AUX_GPIO6H
        329. 8.6.1.329 Register: AUX_GPIO6L
        330. 8.6.1.330 Register: AUX_FACTCORRH
        331. 8.6.1.331 Register: AUX_FACTCORRL
        332. 8.6.1.332 Register: DIE_TEMPH
        333. 8.6.1.333 Register: DIE_TEMPL
        334. 8.6.1.334 Register: AUX_REF3H
        335. 8.6.1.335 Register: AUX_REF3L
        336. 8.6.1.336 Register: AUX_OV_DACH
        337. 8.6.1.337 Register: AUX_OV_DACL
        338. 8.6.1.338 Register: AUX_UV_DACH
        339. 8.6.1.339 Register: AUX_UV_DACL
        340. 8.6.1.340 Register: AUX_OT_DACH
        341. 8.6.1.341 Register: AUX_OT_DACL
        342. 8.6.1.342 Register: AUX_UT_DACH
        343. 8.6.1.343 Register: AUX_UT_DACL
        344. 8.6.1.344 Register: AUX_TWARN_PTATH
        345. 8.6.1.345 Register: AUX_TWARN_PTATL
        346. 8.6.1.346 Register: AUX_DVDDH
        347. 8.6.1.347 Register: AUX_DVDDL
        348. 8.6.1.348 Register: AUX_TSREFH
        349. 8.6.1.349 Register: AUX_TSREFL
        350. 8.6.1.350 Register: AUX_CVDDH
        351. 8.6.1.351 Register: AUX_CVDDL
        352. 8.6.1.352 Register: AUX_AVAO_REFH
        353. 8.6.1.353 Register: AUX_AVAO_REFL
        354. 8.6.1.354 Register: SPI_RX
        355. 8.6.1.355 Register: CB_DONE
        356. 8.6.1.356 Register: GPIO_STAT
        357. 8.6.1.357 Register: CBVC_COMP_STAT
        358. 8.6.1.358 Register: CBVC_VCLOW_STAT
        359. 8.6.1.359 Register: COMM_UART_RC_STAT3
        360. 8.6.1.360 Register: COMM_COML_RC_STAT3
        361. 8.6.1.361 Register: COMM_COMH_RR_STAT3
        362. 8.6.1.362 Register: COMM_COML_RR_STAT3
        363. 8.6.1.363 Register: COMM_COMH_RC_STAT3
        364. 8.6.1.364 Register: COMM_UART_RR_STAT3
        365. 8.6.1.365 Register: COMM_UART_RC_STAT1
        366. 8.6.1.366 Register: COMM_UART_RC_STAT2
        367. 8.6.1.367 Register: COMM_COML_RC_STAT1
        368. 8.6.1.368 Register: COMM_COML_RC_STAT2
        369. 8.6.1.369 Register: COMM_COMH_RR_STAT1
        370. 8.6.1.370 Register: COMM_COMH_RR_STAT2
        371. 8.6.1.371 Register: COMM_UART_TR_STAT1
        372. 8.6.1.372 Register: COMM_UART_TR_STAT2
        373. 8.6.1.373 Register: COMM_COML_TR_STAT1
        374. 8.6.1.374 Register: COMM_COML_TR_STAT2
        375. 8.6.1.375 Register: COMM_COMH_RC_STAT1
        376. 8.6.1.376 Register: COMM_COMH_RC_STAT2
        377. 8.6.1.377 Register: COMM_COML_RR_STAT1
        378. 8.6.1.378 Register: COMM_COML_RR_STAT2
        379. 8.6.1.379 Register: COMM_COMH_TR_STAT1
        380. 8.6.1.380 Register: COMM_COMH_TR_STAT2
        381. 8.6.1.381 Register: COMM_UART_RR_STAT1
        382. 8.6.1.382 Register: COMM_UART_RR_STAT2
        383. 8.6.1.383 Register: OTP_PROG_STAT
        384. 8.6.1.384 Register: OTP_CUST1_STAT1
        385. 8.6.1.385 Register: OTP_CUST1_STAT2
        386. 8.6.1.386 Register: OTP_CUST2_STAT1
        387. 8.6.1.387 Register: OTP_CUST2_STAT2
        388. 8.6.1.388 Register: CB_SW_STAT
        389. 8.6.1.389 Register: GPIO_FAULT
        390. 8.6.1.390 Register: UV_FAULT
        391. 8.6.1.391 Register: OV_FAULT
        392. 8.6.1.392 Register: UT_FAULT
        393. 8.6.1.393 Register: OT_FAULT
        394. 8.6.1.394 Register: TONE_FAULT
        395. 8.6.1.395 Register: COMM_UART_FAULT
        396. 8.6.1.396 Register: COMM_UART_RC_FAULT
        397. 8.6.1.397 Register: COMM_UART_RR_FAULT
        398. 8.6.1.398 Register: COMM_UART_TR_FAULT
        399. 8.6.1.399 Register: COMM_COMH_FAULT
        400. 8.6.1.400 Register: COMM_COMH_RC_FAULT
        401. 8.6.1.401 Register: COMM_COMH_RR_FAULT
        402. 8.6.1.402 Register: COMM_COMH_TR_FAULT
        403. 8.6.1.403 Register: COMM_COML_FAULT
        404. 8.6.1.404 Register: COMM_COML_RC_FAULT
        405. 8.6.1.405 Register: COMM_COML_RR_FAULT
        406. 8.6.1.406 Register: COMM_COML_TR_FAULT
        407. 8.6.1.407 Register: OTP_FAULT
        408. 8.6.1.408 Register: RAIL_FAULT
        409. 8.6.1.409 Register: OVUV_BIST_FAULT
        410. 8.6.1.410 Register: OTUT_BIST_FAULT
        411. 8.6.1.411 Register: ECC_DATAOUT0
        412. 8.6.1.412 Register: ECC_DATAOUT1
        413. 8.6.1.413 Register: ECC_DATAOUT2
        414. 8.6.1.414 Register: ECC_DATAOUT3
        415. 8.6.1.415 Register: ECC_DATAOUT4
        416. 8.6.1.416 Register: ECC_DATAOUT5
        417. 8.6.1.417 Register: ECC_DATAOUT6
        418. 8.6.1.418 Register: ECC_DATAOUT7
        419. 8.6.1.419 Register: ECC_DATAOUT8
        420. 8.6.1.420 Register: SEC_BLK
        421. 8.6.1.421 Register: DED_BLK
        422. 8.6.1.422 Register: DEV_ADD_STAT
        423. 8.6.1.423 Register: COMM_STAT
        424. 8.6.1.424 Register: DAISY_CHAIN_STAT
        425. 8.6.1.425 Register: VCELL1_HU
        426. 8.6.1.426 Register: VCELL1_MU
        427. 8.6.1.427 Register: VCELL1_LU
        428. 8.6.1.428 Register: VCELL2_HU
        429. 8.6.1.429 Register: VCELL2_MU
        430. 8.6.1.430 Register: VCELL2_LU
        431. 8.6.1.431 Register: VCELL3_HU
        432. 8.6.1.432 Register: VCELL3_MU
        433. 8.6.1.433 Register: VCELL3_LU
        434. 8.6.1.434 Register: VCELL4_HU
        435. 8.6.1.435 Register: VCELL4_MU
        436. 8.6.1.436 Register: VCELL4_LU
        437. 8.6.1.437 Register: VCELL5_HU
        438. 8.6.1.438 Register: VCELL5_MU
        439. 8.6.1.439 Register: VCELL5_LU
        440. 8.6.1.440 Register: VCELL6_HU
        441. 8.6.1.441 Register: VCELL6_MU
        442. 8.6.1.442 Register: VCELL6_LU
        443. 8.6.1.443 Register: AUX_BAT_HU
        444. 8.6.1.444 Register: AUX_BAT_LU
        445. 8.6.1.445 Register: AUX_GPIO1_HU
        446. 8.6.1.446 Register: AUX_GPIO1_MU
        447. 8.6.1.447 Register: AUX_GPIO1_LU
        448. 8.6.1.448 Register: AUX_GPIO2_HU
        449. 8.6.1.449 Register: AUX_GPIO2_LU
        450. 8.6.1.450 Register: AUX_GPIO3_HU
        451. 8.6.1.451 Register: AUX_GPIO3_LU
        452. 8.6.1.452 Register: AUX_GPIO4_HU
        453. 8.6.1.453 Register: AUX_GPIO4_LU
        454. 8.6.1.454 Register: AUX_GPIO5_HU
        455. 8.6.1.455 Register: AUX_GPIO5_LU
        456. 8.6.1.456 Register: AUX_GPIO6_HU
        457. 8.6.1.457 Register: AUX_GPIO6_LU
        458. 8.6.1.458 Register: CUST_CRC_RSLTH
        459. 8.6.1.459 Register: CUST_CRC_RSLTL
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Base Device with Measurement Applications Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  LDO Output Bypass
          2. 9.2.1.2.2  Reference Bypass
          3. 9.2.1.2.3  CVDD and VIO Supply Inputs
          4. 9.2.1.2.4  BAT Input
          5. 9.2.1.2.5  LDOIN Supply Input Bypass
          6. 9.2.1.2.6  CB Input
          7. 9.2.1.2.7  VC* Inputs
            1. 9.2.1.2.7.1 Unused VC Inputs (Modules with less than 6 cells)
          8. 9.2.1.2.8  GPIO* Inputs
            1. 9.2.1.2.8.1 Ratiometric Measurement Configuration
            2. 9.2.1.2.8.2 Absolute Measurement Configuration
            3. 9.2.1.2.8.3 Unused GPIO* Inputs
          9. 9.2.1.2.9  UART Communication Bus
          10. 9.2.1.2.10 Daisy-Chain Differential Bus
            1. 9.2.1.2.10.1 Devices on Same PCB
            2. 9.2.1.2.10.2 Devices Separated by Cabling (Not on the Same PCB)
              1. 9.2.1.2.10.2.1 Capacitor Isolation (Not the same PCB)
                1. 9.2.1.2.10.2.1.1 Isolation Capacitor
                2. 9.2.1.2.10.2.1.2 Common-Mode Filter
              2. 9.2.1.2.10.2.2 Transformer Isolation
                1. 9.2.1.2.10.2.2.1 Transformer Specifications
              3. 9.2.1.2.10.2.3 Daisy-Chain Cables
            3. 9.2.1.2.10.3 Daisy Chain System Components
              1. 9.2.1.2.10.3.1 Series Termination Resistance
              2. 9.2.1.2.10.3.2 Bypass Capacitance
              3. 9.2.1.2.10.3.3 Daisy Chain System ESD Protection
            4. 9.2.1.2.10.4 Unused Differential Communications Pins
          11. 9.2.1.2.11 Cell Balancing
            1. 9.2.1.2.11.1 Selecting Cell Balance Resistors
            2. 9.2.1.2.11.2 Differential Filter Capacitor Selection
            3. 9.2.1.2.11.3 Cell Balancing External MOSFET Selection (optional)
          12. 9.2.1.2.12 Post-Assembly Calibration
            1. 9.2.1.2.12.1 Cell ADC Post-Assembly Calibration
              1. 9.2.1.2.12.1.1 Gain Error Correction
              2. 9.2.1.2.12.1.2 Offset Error Correction
            2. 9.2.1.2.12.2 GPIO* Post-Assembly Calibration
          13. 9.2.1.2.13 Device Addressing
            1. 9.2.1.2.13.1 NVM Stored Address
            2. 9.2.1.2.13.2 Auto Addressing
            3. 9.2.1.2.13.3 GPIO Addressing
          14. 9.2.1.2.14 Calculating Wakeup Timing
            1. 9.2.1.2.14.1 Wakeup Timing in SHUTDOWN Mode (or Initial Powerup)
            2. 9.2.1.2.14.2 Wakeup Timing in SLEEP Mode
              1. 9.2.1.2.14.2.1 Wake Up Command
              2. 9.2.1.2.14.2.2 SLEEPtoACTIVE command
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Bridge Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Capacitor Isolated System
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Transformer Isolated System
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
      5. 9.2.5 Multi-Drop System
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
        3. 9.2.5.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Communication Bridge System
    2. 10.2 Integrated Base Device System
    3. 10.3 Multi-Drop System
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Differential Communication
      3. 11.1.3 Power Supplies and Reference
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resource
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

PHP Package
48-Pin PQFP
Top View
BQ79606A-Q1 pinout.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AVSS 15 GND Analog Ground. Pin 15 is not connected to pin 45 internally. Ground connection for internal analog circuits. Connect CVSS, DVSS, and AVSS externally. AVSS must NOT be left unconnected.
45 GND Analog Ground. Pin 45 is not connected to pin 15 internally. Ground connection for internal ADC circuits. Connect the decoupling capacitor of the REF1 to this pin. Connect CVSS, DVSS, and AVSS externally. AVSS must NOT be left unconnected.
AVDD 44 O 5-V Regulator Output. AVDD supplies internal circuits. Bypass AVDD to AVSS with 2.2µF/10V ceramic capacitor. The capacitance range after derating must fall between 1uF to 2.2uF. Do not connect additional load to AVDD.
BAT 48 I Battery Stack Connection. Connect BAT to the positive terminal of the highest cell in the stack through a 100Ω resistor. Bypass BAT to AVSS with a 0.33µF/50V capacitor.
CB0 13 I/O Cell Balance Connection 0. CB0 is connected to the internal balance FET. Connect CB0 to the negative terminal of cell 1 (bottom cell) through a resistor. The resistor sets the balance current. See Selecting Cell Balance Resistors for details on calculating the resistor value. Additionally, connect a 0.47µF, 10V (or better) ceramic capacitor between CB0 and AVSS.
CB1 11 I/O Cell Balance Connection 1. CB1 is connected to the internal balance FET. Connect CB1 to the junction of the positive terminal of cell 1 (bottom cell) and the negative terminal of cell 2 through a resistor. The resistor sets the balance current. See Selecting Cell Balance Resistors for details on calculating the resistor value. Additionally, connect a 0.47µF, 10V (or better) ceramic capacitor between CB1 and CB0. Short CB1 to CB0 if cell balancing is not used.
CB2 9 I/O Cell Balance Connection 2. CB2 is connected to the internal balance FET. Connect CB2 to the junction of the positive terminal of cell 2 and the negative terminal of cell 3 through a resistor. The resistor sets the balance current. See Selecting Cell Balance Resistors for details on calculating the resistor value. Additionally, connect a 0.8µF, 10V (or better) ceramic capacitor between CB2 and CB1. Short CB2 to CB1 if cell balancing is not used.
CB3 7 I/O Cell Balance Connection 3. CB3 is connected to the internal balance FET. Connect CB3 to the junction of the positive terminal of cell 3 and the negative terminal of cell 4 through a resistor. The resistor sets the balance current. See Selecting Cell Balance Resistors for details on calculating the resistor value. Additionally, connect a 1-µF, 10V (or better) ceramic capacitor between CB3 and CB2. Short CB3 to CB2 if cell balancing is not used.
CB4 5 I/O Cell Balance Connection 4. CB4 is connected to the internal balance FET. Connect CB4 to the junction of the positive terminal of cell 4 and the negative terminal of cell 5 through a resistor. The resistor sets the balance current. See Selecting Cell Balance Resistors for details on calculating the resistor value. Additionally, connect a 1-µF, 10V (or better) ceramic capacitor between CB4 and CB3. Short CB4 to CB3 if cell balancing is not used.
CB5 3 I/O Cell Balance Connection 5. CB5 is connected to the internal balance FET. Connect CB5 to the junction of the positive terminal of cell 5 and the negative terminal of cell 6 through a resistor. The resistor sets the balance current. See Selecting Cell Balance Resistors for details on calculating the resistor value. Additionally, connect a 0.8µF, 10V (or better) ceramic capacitor between CB5 and CB4. Short CB5 to CB4 if cell balancing is not used.
CB6 1 I/O Cell Balance Connection 6. CB6 is connected to the internal balance FET. Connect CB6 to the positive terminal of cell 6 through a resistor. The resistor sets the balance current. See Selecting Cell Balance Resistors for details on calculating the resistor value. Additionally, connect a 0.47µF, 10V (or better) ceramic capacitor between CB6 and CB5. Short CB6 to CB5 if cell balancing is not used.
COMHN 21 I/O This is AC coupled I/O. Daisy Chain Communication Connections for Higher Stack Device. COMHP and COMHN provide differential communications for the daisy chain interface. Connect COMHP and COMHN to the COMLP and COMLN inputs on the next higher device in the stack. For devices separated by twisted pair cabling, the connections must be made through either capacitor or transformer isolation network. See Daisy-Chain Differential Bus for details. Leave COMH* unconnected if not used.
COMHP 22 I/O
COMLN 20 I/O This is AC coupled I/O. Daisy Chain Communication Connections for Lower Stack Device. COMLP and COMLN provide differential communication for the daisy chain interface. Connect COMLP and COMLN to the COMHP and COMHN inputs on the next lower device in the stack. For devices separated by twisted pair cabling, the connections must be made through either capacitor or transformer isolation network. SeeDaisy-Chain Differential Bus section for details. Leave COML* unconnected if not used.
COMLP 19 I/O
CVDD 25 I Daisy Chain Communication Power. CVDD is the supply input for the stack daisy chain communication transceiver circuits. Connect CVDD to VLDO through a 0Ω resistor. Bypass CVDD to CVSS with a 2.2µF/10V ceramic capacitor. The capacitance range after derating must fall between 1uF to 2.2uF (Excluding VLDO cap).
CVSS 26 GND Daisy Chain Communication Ground. Ground connection for internal daisy chain transceivers. Connect AVSS, CVSS, and DVSS externally. CVSS must NOT be left unconnected.
DVDD 36 O 1.8-V Regulator Output. DVDD supplies internal circuits. Bypass DVDD to DVSS with a ceramic capacitor ranging from 1uF to 2.2µF with 10V rating. The capacitance range after derating must fall between 1uF to 2.2uF. Connect the capacitor as close as possible to the pin with a noise free trace. Do not connect additional load to DVDD.
DVSS 35 GND Digital Ground. Ground connection for internal digital logic. Connect AVSS, CVSS, and DVSS externally. DVSS must NOT be left unconnected.
FAULTLP 17 O This is AC coupled I/O. Daisy Chain Fault Connections for Lower Stack Device. FAULTLN and FAULTLP provide differential fault signaling for the daisy chain interface. Connect FAULTLP and FAULTLN to the FAULTHP and FAULTHN inputs on the next lower device in the stack. For devices separated by twisted pair cabling, the connections must be made through either capacitor or transformer isolation network. See Daisy-Chain Differential Bus for details. Leave FAULTL* unconnected if not used.
FAULTLN 18 O
FAULTHP 24 I This is AC coupled I/O. Daisy Chain Fault Connections for Higher Stack Device. FAULTHN and FAULTHP provide differential communication signaling for the daisy chain interface. Connect FAULTHP and FAULTHN to the FAULTLP and FAULTLN inputs on the next higher device in the stack. For devices separated by twisted pair cabling, the connections must be made through either capacitor or transformer isolation network. See Daisy-Chain Differential Bus section for details. Leave FAULTH* unconnected if not used.
FAULTHN 23 I
GPIO1 27 I/O General Purpose Input/Output. GPIO* is configurable as an input or output. GPIO* has configurable pullup and pulldown (weak) resistors. In input mode, GPIO* is configurable to indicate a fault on a high or low, or simply update register to indicate input level. Additionally, GPIO1-GPIO6 are configurable as an ADC input to measure an external temperature sensor (NTC) or other DC voltage. To monitor an external temperature sensor, connect a resistor divider from TSREF to AVSS with GPIO* connected to the center tap. The ADC reports a ratiometric result of GPIO*/TSREF. To measure a standard DC voltage, no resistor divider is required. When configured as an ADC input, GPIO1-GPIO6 support under temperature and over temperature hardware protection as well. See the GPIO* Inputs for details on calculating the component values. GPIO1-GPIO6 also are available to be used for the programming the device address. This is most commonly used in multi-drop. Connect GPIO* to AVSS through a 10-kΩ resistor if unused.
GPIO2 28 I/O
GPIO3 29 I/O
GPIO4 30 I/O
GPIO5 31 I/O
GPIO6 32 I/O
LDOIN 37 I LDO Supply. LDOIN supplies the internal LDO regulators. Connect LDOIN to the positive terminal of the highest cell in the stack through a 40Ω to 50Ω resistor. Bypass LDOIN to AVSS with a 0.33µF/50V capacitor.
N.C. 47 - No Connect. No internal connection. Leave N.C. unconnected on the board.
38 -
NFAULT 42 O Active-Low Fault Indication Output. NFAULT pulls low to indicate to the external host that a fault condition has occurred. NFAULT is an open-drain output. Connect a 10KΩ to 100kΩ resistor from NFAULT to VIO. Leave NFAULT unconnected if not used.
REF1 46 O High-Power Reference Bypass Connection. Bypass REF1 to AVSS (pin 45) with a 2.2µF (10V) ceramic capacitor. The capacitance range after derating must fall between 0.5uF to 2.2uF. Do not connect additional load to REF1. Put the cap as close as possible to the REF1 and AVSS pins and make sure the trace is noise free.
RX 41 I UART Receiver Input. Connect a 10KΩ to 100kΩ pull up resistor from RX to VIO and connect RX to the TX output of the host micro-controller. If unused, connect RX to VIO. RX must not be left unconnected.
TSREF 43 O Bias Voltage for NTC Monitor. Bypass TSREF to AVSS with a 2.2µF (10V or better) ceramic capacitor. The capacitance range after derating must fall between 1uF to 2.2uF. Connect TSREF to the top of the resistor divider network for the GPIOs when used in NTC monitor mode. TSREF is not available to drive any load other than the resistor network. Leave TSREF unconnected if NTC monitoring is not used.
TX 40 O UART Transmitter Output. Connect TX to the RX input of the host micro-controller. For base devices, the TX must be pulled high on the host-side. Leave it floating if unused for stack configuration.
VC0 14 I Cell Voltage Sense Connection 0. Connect VC0 to the negative terminal of cell 1 (bottom cell) through a resistor. See the VC* Inputs section for details on selecting the resistor value. Connect a 0.47µF, 10V (or better) ceramic capacitor from VC0 to AVSS.
VC1 12 I Cell Voltage Sense Connection 1. Connect VC1 to the junction of the positive terminal of cell 1 (bottom cell) and the negative terminal of cell 2 through a resistor. See the VC* Inputs section for details on selecting the resistor value. Connect a 0.47µF, 10V (or better) ceramic capacitor from VC1 to VC0.
VC2 10 I Cell Voltage Sense Connection 2. Connect VC2 to the junction of the positive terminal of cell 2 and the negative terminal of cell 3 through a resistor. See the VC* Inputs section for details on selecting the resistor value. Recommend to connect a 0.8µF for better transient response, 10V (or better) ceramic capacitor from VC2 to VC1.
VC3 8 I Cell Voltage Sense Connection 3. Connect VC3 to the junction of the positive terminal of cell 3 and the negative terminal of cell 4 through a resistor. See the VC* Inputs section for details on selecting the resistor value. Recommend to connect a 1-µF for better transient response, 10V (or better) ceramic capacitor from VC3 to VC2.
VC4 6 I Cell Voltage Sense Connection 4. Connect VC4 to the junction of the positive terminal of cell 4 and the negative terminal of cell 5 through a resistor. See the VC* Inputs section for details on selecting the resistor value. Recommend to connect a 1-µF for better transient response, 10V (or better) ceramic capacitor from VC4 to VC3.
VC5 4 I Cell Voltage Sense Connection 5. Connect VC5 to the junction of the positive terminal of cell 5 and the negative terminal of cell 6 through a resistor. See the VC* Inputs section for details on selecting the resistor value. Recommend to connect a 0.8µF for better transient response, 10V (or better) ceramic capacitor from VC5 to VC4.
VC6 2 I Cell Voltage Sense Connection 6. Connect VC6 to the positive terminal of cell 6 through a resistor. See the VC* Inputs section for details on selecting the resistor value. Connect a 0.47µF, 10V (or better) ceramic capacitor from VC6 to VC5.
VIO 33 I I/O Supply Voltage. All of the digital pins (WAKEUP, RX, TX and GPIO's) are referenced to VIO. Connect VIO to the system rail between 1.8V and 5.25V. VIO is supplied from the external system logic supply or is connected to VLDO or CVDD for stack devices (or systems without a logic supply). Bypass VIO to AVSS with a 2.2µF/10V ceramic capacitor.
VLDO 39 O 5-V Regulator Output. VLDO supplies CVDD (can be used for VIO). Bypass VLDO to AVSS with ceramic capacitor of typical value of 2.2µF/10V. The total range of the capacitance after derating can be from 1uF to 2.2uF (Excluding the CVDD cap). The start up time will increase with higher cap value of more than 2.2uF. Do not connect additional load to VLDO.
VPROG 34 I OTP Programming Voltage. Connect 7.6 V to VPROG during OTP programming with 1uF/16V capacitor to GND. If not used, connected it to GND through a 100KΩ resistor.
WAKEUP 16 I Wake Input for Base Device. Use WAKEUP to send WAKE and SHUTDOWN commands to devices in stand alone operation, multi-drop stacks, or the base device in a daisy chain stack. See the Base Device Wakeup and Hardware Shutdown section for details on the process for sending the commands. WAKEUP must be pulled high during normal operation to configure the device as a base device. For stack devices, connect WAKEUP to AVSS. Do NOT leave WAKEUP unconnected.