SLUSDV2B May   2020  – January 2023 BQ25798

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power-On-Reset
      2. 9.3.2  PROG Pin Configuration
      3. 9.3.3  Device Power Up from Battery without Input Source
      4. 9.3.4  Device Power Up from Input Source
        1. 9.3.4.1 Power Up REGN LDO
        2. 9.3.4.2 Poor Source Qualification
        3. 9.3.4.3 ILIM_HIZ Pin
        4. 9.3.4.4 Default VINDPM Setting
        5. 9.3.4.5 Input Source Type Detection
          1. 9.3.4.5.1 D+/D– Detection Sets Input Current Limit
          2. 9.3.4.5.2 HVDCP Detection Procedure
          3. 9.3.4.5.3 Connector Fault Detection
      5. 9.3.5  Dual-Input Power Mux
        1. 9.3.5.1 ACDRV Turn On Condition
        2. 9.3.5.2 VBUS Input Only
        3. 9.3.5.3 One ACFET-RBFET
        4. 9.3.5.4 Two ACFETs-RBFETs
      6. 9.3.6  Buck-Boost Converter Operation
        1. 9.3.6.1 Force Input Current Limit Detection
        2. 9.3.6.2 Input Current Optimizer (ICO)
        3. 9.3.6.3 Maximum Power Point Tracking for Small PV Panel
        4. 9.3.6.4 Pulse Frequency Modulation (PFM)
        5. 9.3.6.5 Device HIZ State
      7. 9.3.7  USB On-The-Go (OTG)
        1. 9.3.7.1 OTG Mode to Power External Devices
        2. 9.3.7.2 Backup Power Supply Mode
        3. 9.3.7.3 Backup Mode with Dual Input Mux
      8. 9.3.8  Power Path Management
        1. 9.3.8.1 Narrow VDC Architecture
        2. 9.3.8.2 Dynamic Power Management
      9. 9.3.9  Battery Charging Management
        1. 9.3.9.1 Autonomous Charging Cycle
        2. 9.3.9.2 Battery Charging Profile
        3. 9.3.9.3 Charging Termination
        4. 9.3.9.4 Charging Safety Timer
        5. 9.3.9.5 Thermistor Qualification
          1. 9.3.9.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.3.9.5.2 Cold/Hot Temperature Window in OTG Mode
      10. 9.3.10 Integrated 16-Bit ADC for Monitoring
      11. 9.3.11 Status Outputs ( STAT, and INT)
        1. 9.3.11.1 Charging Status Indicator (STAT Pin)
        2. 9.3.11.2 Interrupt to Host ( INT)
      12. 9.3.12 Ship FET Control
        1. 9.3.12.1 Shutdown Mode
        2. 9.3.12.2 Ship Mode
        3. 9.3.12.3 System Power Reset
      13. 9.3.13 Protections
        1. 9.3.13.1 Voltage and Current Monitoring
          1. 9.3.13.1.1  VAC Over-voltage Protection (VAC_OVP)
          2. 9.3.13.1.2  VBUS Over-voltage Protection (VBUS_OVP)
          3. 9.3.13.1.3  VBUS Under-voltage Protection (POORSRC)
          4. 9.3.13.1.4  System Over-voltage Protection (VSYS_OVP)
          5. 9.3.13.1.5  System Short Protection (VSYS_SHORT)
          6. 9.3.13.1.6  Battery Over-voltage Protection (VBAT_OVP)
          7. 9.3.13.1.7  Battery Over-current Protection (IBAT_OCP)
          8. 9.3.13.1.8  Input Over-current Protection (IBUS_OCP)
          9. 9.3.13.1.9  OTG Over-voltage Protection (OTG_OVP)
          10. 9.3.13.1.10 OTG Under-voltage Protection (OTG_UVP)
        2. 9.3.13.2 Thermal Regulation and Thermal Shutdown
      14. 9.3.14 Serial Interface
        1. 9.3.14.1 Data Validity
        2. 9.3.14.2 START and STOP Conditions
        3. 9.3.14.3 Byte Format
        4. 9.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.3.14.5 Target Address and Data Direction Bit
        6. 9.3.14.6 Single Write and Read
        7. 9.3.14.7 Multi-Write and Multi-Read
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
      2. 9.4.2 Register Bit Reset
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PV Panel Selection
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input (VBUS / PMID) Capacitor
        4. 10.2.2.4 Output (VSYS) Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9.5.1 I2C Registers

Table 9-12 lists the I2C registers. All register offset addresses not listed in Table 9-12 should be considered as reserved locations and the register contents should not be modified.

Table 9-12 I2C Registers
Offset Acronym Register Name Section
0h REG00_Minimal_System_Voltage Minimal System Voltage Section 9.5.1.1
1h REG01_Charge_Voltage_Limit Charge Voltage Limit Section 9.5.1.2
3h REG03_Charge_Current_Limit Charge Current Limit Section 9.5.1.3
5h REG05_Input_Voltage_Limit Input Voltage Limit Section 9.5.1.4
6h REG06_Input_Current_Limit Input Current Limit Section 9.5.1.5
8h REG08_Precharge_Control Precharge Control Section 9.5.1.6
9h REG09_Termination_Control Termination Control Section 9.5.1.7
Ah REG0A_Re-charge_Control Re-charge Control Section 9.5.1.8
Bh REG0B_VOTG_regulation VOTG regulation Section 9.5.1.9
Dh REG0D_IOTG_regulation IOTG regulation Section 9.5.1.10
Eh REG0E_Timer_Control Timer Control Section 9.5.1.11
Fh REG0F_Charger_Control_0 Charger Control 0 Section 9.5.1.12
10h REG10_Charger_Control_1 Charger Control 1 Section 9.5.1.13
11h REG11_Charger_Control_2 Charger Control 2 Section 9.5.1.14
12h REG12_Charger_Control_3 Charger Control 3 Section 9.5.1.15
13h REG13_Charger_Control_4 Charger Control 4 Section 9.5.1.16
14h REG14_Charger_Control_5 Charger Control 5 Section 9.5.1.17
15h REG15_MPPT_Control MPPT Control Section 9.5.1.18
16h REG16_Temperature_Control Temperature Control Section 9.5.1.19
17h REG17_NTC_Control_0 NTC Control 0 Section 9.5.1.20
18h REG18_NTC_Control_1 NTC Control 1 Section 9.5.1.21
19h REG19_ICO_Current_Limit ICO Current Limit Section 9.5.1.22
1Bh REG1B_Charger_Status_0 Charger Status 0 Section 9.5.1.23
1Ch REG1C_Charger_Status_1 Charger Status 1 Section 9.5.1.24
1Dh REG1D_Charger_Status_2 Charger Status 2 Section 9.5.1.25
1Eh REG1E_Charger_Status_3 Charger Status 3 Section 9.5.1.26
1Fh REG1F_Charger_Status_4 Charger Status 4 Section 9.5.1.27
20h REG20_FAULT_Status_0 FAULT Status 0 Section 9.5.1.28
21h REG21_FAULT_Status_1 FAULT Status 1 Section 9.5.1.29
22h REG22_Charger_Flag_0 Charger Flag 0 Section 9.5.1.30
23h REG23_Charger_Flag_1 Charger Flag 1 Section 9.5.1.31
24h REG24_Charger_Flag_2 Charger Flag 2 Section 9.5.1.32
25h REG25_Charger_Flag_3 Charger Flag 3 Section 9.5.1.33
26h REG26_FAULT_Flag_0 FAULT Flag 0 Section 9.5.1.34
27h REG27_FAULT_Flag_1 FAULT Flag 1 Section 9.5.1.35
28h REG28_Charger_Mask_0 Charger Mask 0 Section 9.5.1.36
29h REG29_Charger_Mask_1 Charger Mask 1 Section 9.5.1.37
2Ah REG2A_Charger_Mask_2 Charger Mask 2 Section 9.5.1.38
2Bh REG2B_Charger_Mask_3 Charger Mask 3 Section 9.5.1.39
2Ch REG2C_FAULT_Mask_0 FAULT Mask 0 Section 9.5.1.40
2Dh REG2D_FAULT_Mask_1 FAULT Mask 1 Section 9.5.1.41
2Eh REG2E_ADC_Control ADC Control Section 9.5.1.42
2Fh REG2F_ADC_Function_Disable_0 ADC Function Disable 0 Section 9.5.1.43
30h REG30_ADC_Function_Disable_1 ADC Function Disable 1 Section 9.5.1.44
31h REG31_IBUS_ADC IBUS ADC Section 9.5.1.45
33h REG33_IBAT_ADC IBAT ADC Section 9.5.1.46
35h REG35_VBUS_ADC VBUS ADC Section 9.5.1.47
37h REG37_VAC1_ADC VAC1 ADC Section 9.5.1.48
39h REG39_VAC2_ADC VAC2 ADC Section 9.5.1.49
3Bh REG3B_VBAT_ADC VBAT ADC Section 9.5.1.50
3Dh REG3D_VSYS_ADC VSYS ADC Section 9.5.1.51
3Fh REG3F_TS_ADC TS ADC Section 9.5.1.52
41h REG41_TDIE_ADC TDIE_ADC Section 9.5.1.53
43h REG43_D+_ADC D+ ADC Section 9.5.1.54
45h REG45_D-_ADC D- ADC Section 9.5.1.55
47h REG47_DPDM_Driver DPDM Driver Section 9.5.1.56
48h REG48_Part_Information Part Information Section 9.5.1.57

Complex bit access types are encoded to fit into small table cells. The following table shows the codes that are used for access types in this section.

Table 9-13 I2C Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Others
Range The register bits are only valid in this defined range.
Clamped Low Any write on the register lower than the minimal value of the valid range, will be ignored by the charger
Clamped High Any write on the register higher than the maximum value of the valid range, will be ignored by the charger

9.5.1.1 REG00_Minimal_System_Voltage Register (Offset = 0h) [reset = X]

REG00_Minimal_System_Voltage is shown in Figure 9-26 and described in Table 9-14.

Return to the Summary Table.

Minimal System Voltage

Figure 9-26 REG00_Minimal_System_Voltage Register
7 6 5 4 3 2 1 0
RESERVED VSYSMIN_5:0
R/W-0h R/W-X
Table 9-14 REG00_Minimal_System_Voltage Register Field Descriptions
Bit Field Type Reset Notes Description
7-6 RESERVED R/W 0h RESERVED
5-0 VSYSMIN_5:0 R/W X Reset by:
REG_RST
 Minimal System Voltage:
During POR, the device reads the resistance tie to PROG pin, to identify the default battery cell count and determine the default power on VSYSMIN list below:
1s: 3.5V
2s: 7V
3s: 9V
4s: 12V
Type : RW
Range : 2500mV-16000mV
Fixed Offset : 2500mV
Bit Step Size : 250mV
Clamped High

9.5.1.2 REG01_Charge_Voltage_Limit Register (Offset = 1h) [reset = X]

REG01_Charge_Voltage_Limit is shown in Figure 9-27 and described in Table 9-15.

Return to the Summary Table.

Charge Voltage Limit

Figure 9-27 REG01_Charge_Voltage_Limit Register
15 14 13 12 11 10 9 8
RESERVED VREG_10:0
R-0h R/W-X
7 6 5 4 3 2 1 0
VREG_10:0
R/W-X
Table 9-15 REG01_Charge_Voltage_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15-11 RESERVED R 0h RESERVED
10-0 VREG_10:0 R/W X Reset by:
REG_RST
 Battery Voltage Limit:
During POR, the device reads the resistance tie to PROG pin, to identify the default battery cell count and determine the default power-on battery voltage regulation limit:
1s: 4.2V
2s: 8.4V
3s: 12.6V
4s: 16.8V
Type : RW
Range : 3000mV-18800mV
Fixed Offset : 0mV
Bit Step Size : 10mV
Clamped Low

9.5.1.3 REG03_Charge_Current_Limit Register (Offset = 3h) [reset = X]

REG03_Charge_Current_Limit is shown in Figure 9-28 and described in Table 9-16.

Return to the Summary Table.

Charge Current Limit

Figure 9-28 REG03_Charge_Current_Limit Register
15 14 13 12 11 10 9 8
RESERVED ICHG_8:0
R-0h R/W-X
7 6 5 4 3 2 1 0
ICHG_8:0
R/W-X
Table 9-16 REG03_Charge_Current_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15-9 RESERVED R 0h RESERVED
8-0 ICHG_8:0 R/W X Reset by:
WATCHDOG
REG_RST
 Charge Current Limit
During POR, the device reads the resistance tie to PROG pin, to identify the default battery cell count and determine the default power-on battery charging current: 1A
Type : RW
Range : 50mA-5000mA
Fixed Offset : 0mA
Bit Step Size : 10mA
Clamped Low

9.5.1.4 REG05_Input_Voltage_Limit Register (Offset = 5h) [reset = 24h]

REG05_Input_Voltage_Limit is shown in Figure 9-29 and described in Table 9-17.

Return to the Summary Table.

Input Voltage Limit

Figure 9-29 REG05_Input_Voltage_Limit Register
7 6 5 4 3 2 1 0
VINDPM_7:0
R/W-24h
Table 9-17 REG05_Input_Voltage_Limit Register Field Descriptions
Bit Field Type Reset Description
7-0 VINDPM_7:0 R/W 24h

Absolute VINDPM Threshold
VINDPM register is reset to 3600mV upon adapter unplugged and it is set to the value based on the VBUS measurement when the adapter plugs in. It is not reset by the REG_RST and the WATCHDOG
Type : RW
POR: 3600mV (24h)
Range : 3600mV-22000mV
Fixed Offset : 0mV
Bit Step Size : 100mV
Clamped Low

9.5.1.5 REG06_Input_Current_Limit Register (Offset = 6h) [reset = 12Ch]

REG06_Input_Current_Limit is shown in Figure 9-30 and described in Table 9-18.

Return to the Summary Table.

Input Current Limit

Figure 9-30 REG06_Input_Current_Limit Register
15 14 13 12 11 10 9 8
RESERVED IINDPM_8:0
R-0h R/W-12Ch
7 6 5 4 3 2 1 0
IINDPM_8:0
R/W-12Ch
Table 9-18 REG06_Input_Current_Limit Register Field Descriptions
Bit Field Type Reset Notes Description
15-9 RESERVED R 0h RESERVED
8-0 IINDPM_8:0 R/W 12Ch Reset by:
REG_RST
 Based on D+/D- detection results:
USB SDP = 500mA
USB CDP = 1.5A
USB DCP = 3.25A
Adjustable High Voltage DCP = 1.5A
Unknown Adapter = 3A
Non-Standard Adapter = 1A/2A/2.1A/2.4A
Type : RW
POR: 3000mA (12Ch)
Range : 100mA-3300mA
Fixed Offset : 0mA
Bit Step Size : 10mA
Clamped Low

9.5.1.6 REG08_Precharge_Control Register (Offset = 8h) [reset = C3h]

REG08_Precharge_Control is shown in Figure 9-31 and described in Table 9-19.

Return to the Summary Table.

Precharge Control

Figure 9-31 REG08_Precharge_Control Register
7 6 5 4 3 2 1 0
VBAT_LOWV_1:0 IPRECHG_5:0
R/W-3h R/W-3h
Table 9-19 REG08_Precharge_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7-6 VBAT_LOWV_1:0 R/W 3h Reset by:
REG_RST
 Battery voltage thresholds for the transition from precharge to fast charge, which is defined as a ratio of battery regulation limit (VREG)
Type : RW
POR: 11b

0h = 15%*VREG

1h = 62.2%*VREG

2h = 66.7%*VREG

3h = 71.4%*VREG
5-0 IPRECHG_5:0 R/W 3h Reset by:
WATCHDOG
REG_RST
 Precharge current limit
Type : RW
POR: 120mA (3h)
Range : 40mA-2000mA
Fixed Offset : 0mA
Bit Step Size : 40mA
Clamped Low

9.5.1.7 REG09_Termination_Control Register (Offset = 9h) [reset = 5h]

REG09_Termination_Control is shown in Figure 9-32 and described in Table 9-20.

Return to the Summary Table.

Termination Control

Figure 9-32 REG09_Termination_Control Register
7 6 5 4 3 2 1 0
RESERVED REG_RST RESERVED ITERM_4:0
R-0h R/W-0h R-0h R/W-5h
Table 9-20 REG09_Termination_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7 RESERVED R 0h RESERVED
6 REG_RST R/W 0h Reset registers to default values and reset timer
Type : RW
POR: 0b

0h = Not reset

1h = Reset
5 STOP_WD_CHG RW 0h Defines whether a watchdog timer expiration will disable charging
Type: RW
POR: 0b0h = WD timer expiration keeps existing EN_CHG setting

1h = WD timer expiration sets EN_CHG=0
4-0 ITERM_4:0 R/W 5h Reset by:
WATCHDOG
REG_RST
 Termination current
Type : RW
POR: 200mA (5h)
Range : 40mA-1000mA
Fixed Offset : 0mA
Bit Step Size : 40mA
Clamped Low

9.5.1.8 REG0A_Re-charge_Control Register (Offset = Ah) [reset = X]

REG0A_Re-charge_Control is shown in Figure 9-33 and described in Table 9-21.

Return to the Summary Table.

Re-charge Control

Figure 9-33 REG0A_Re-charge_Control Register
7 6 5 4 3 2 1 0
CELL_1:0 TRECHG_1:0 VRECHG_3:0
R/W-X R/W-2h R/W-3h
Table 9-21 REG0A_Re-charge_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7-6 CELL_1:0 R/W X At POR, the charger reads the PROG pin resistance to determine the battery cell count and update this CELL bits accordingly.
Type : RW

0h = 1s

1h = 2s

2h = 3s

3h = 4s
5-4 TRECHG_1:0 R/W 2h Reset by:
WATCHDOG
REG_RST
 Battery recharge deglich time
Type : RW
POR: 10b

0h = 64ms

1h = 256ms

2h = 1024ms (default)

3h = 2048ms
3-0 VRECHG_3:0 R/W 3h Reset by:
WATCHDOG
REG_RST
 Battery Recharge Threshold Offset (Below VREG)
Type : RW
POR: 200mV (3h)
Range : 50mV-800mV
Fixed Offset : 50mV
Bit Step Size : 50mV

9.5.1.9 REG0B_VOTG_regulation Register (Offset = Bh) [reset = DCh]

REG0B_VOTG_regulation is shown in Figure 9-34 and described in Table 9-22.

Return to the Summary Table.

VOTG regulation

Figure 9-34 REG0B_VOTG_regulation Register
15 14 13 12 11 10 9 8
RESERVED VOTG_10:0
R-0h R/W-DCh
7 6 5 4 3 2 1 0
VOTG_10:0
R/W-DCh
Table 9-22 REG0B_VOTG_regulation Register Field Descriptions
Bit Field Type Reset Notes Description
15-11 RESERVED R 0h RESERVED
10-0 VOTG_10:0 R/W DCh Reset by:
WATCHDOG
REG_RST
 OTG mode regulation voltage
Type : RW
POR: 5000mV (DCh)
Range : 2800mV-22000mV
Fixed Offset : 2800mV
Bit Step Size : 10mV
Clamped High

9.5.1.10 REG0D_IOTG_regulation Register (Offset = Dh) [reset = 4Bh]

REG0D_IOTG_regulation is shown in Figure 9-35 and described in Table 9-23.

Return to the Summary Table.

IOTG regulation

Figure 9-35 REG0D_IOTG_regulation Register
7 6 5 4 3 2 1 0
PRECHG_TMR IOTG_6:0
R/W-0h R/W-4Bh
Table 9-23 REG0D_IOTG_regulation Register Field Descriptions
Bit Field Type Reset Notes Description
7 PRECHG_TMR R/W 0h Reset by:
WATCHDOG
REG_RST
 Pre-charge safety timer setting
Type : RW
POR: 0b

0h = 2 hrs (default)

1h = 0.5 hrs
6-0 IOTG_6:0 R/W 4Bh Reset by:
WATCHDOG
REG_RST
 OTG current limit
Type : RW
POR: 3040mA (4Bh)
Range : 160mA-3360mA
Fixed Offset : 0mA
Bit Step Size : 40mA
Clamped Low

9.5.1.11 REG0E_Timer_Control Register (Offset = Eh) [reset = 3Dh]

REG0E_Timer_Control is shown in Figure 9-36 and described in Table 9-24.

Return to the Summary Table.

Timer Control

Figure 9-36 REG0E_Timer_Control Register
7 6 5 4 3 2 1 0
TOPOFF_TMR_1:0 EN_TRICHG_TMR EN_PRECHG_TMR EN_CHG_TMR CHG_TMR_1:0 TMR2X_EN
R/W-0h R/W-1h R/W-1h R/W-1h R/W-2h R/W-1h
Table 9-24 REG0E_Timer_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7-6 TOPOFF_TMR_1:0 R/W 0h Reset by:
WATCHDOG
REG_RST
 Top-off timer control
Type : RW
POR: 00b

0h = Disabled (default)

1h = 15 mins

2h = 30 mins

3h = 45 mins
5 EN_TRICHG_TMR R/W 1h Reset by:
WATCHDOG
REG_RST
 Enable trickle charge timer (fixed as 1hr)
Type : RW
POR: 1b

0h = Disabled

1h = Enabled (default)
4 EN_PRECHG_TMR R/W 1h Reset by:
WATCHDOG
REG_RST
 Enable pre-charge timer
Type : RW
POR: 1b

0h = Disabled

1h = Enabled (default)
3 EN_CHG_TMR R/W 1h Reset by:
WATCHDOG
REG_RST
 Enable fast charge timer
Type : RW
POR: 1b

0h = Disabled

1h = Enabled (default)
2-1 CHG_TMR_1:0 R/W 2h Reset by:
WATCHDOG
REG_RST
 Fast charge timer setting
Type : RW
POR: 10b

0h = 5 hrs

1h = 8 hrs

2h = 12 hrs (default)

3h = 24 hrs
0 TMR2X_EN R/W 1h Reset by:
WATCHDOG
REG_RST
 TMR2X_EN
Type : RW
POR: 1b

0h = Trickle charge, pre-charge and fast charge timer NOT slowed by 2X during input DPM or thermal regulation.

1h = Trickle charge, pre-charge and fast charge timer slowed by 2X during input DPM or thermal regulation (default)

9.5.1.12 REG0F_Charger_Control_0 Register (Offset = Fh) [reset = A2h]

REG0F_Charger_Control_0 is shown in Figure 9-37 and described in Table 9-25.

Return to the Summary Table.

Charger Control 0

Figure 9-37 REG0F_Charger_Control_0 Register
7 6 5 4 3 2 1 0
EN_AUTO_IBATDIS FORCE_IBATDIS EN_CHG EN_ICO FORCE_ICO EN_HIZ EN_TERM EN_BACKUP
R/W-1h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h
R-0h
Table 9-25 REG0F_Charger_Control_0 Register Field Descriptions
Bit Field Type Reset Notes Description
7 EN_AUTO_IBATDIS R/W 1h Reset by:
REG_RST
 Enable the auto battery discharging during the battery OVP fault
Type : RW
POR: 1b

0h = The charger will NOT apply a discharging current on BAT during battery OVP

1h = The charger will apply a discharging current on BAT during battery OVP
6 FORCE_IBATDIS R/W 0h Reset by:
REG_RST
 Force a battery discharging current
Type : RW
POR: 0b

0h = IDLE (default)

1h = Force the charger to apply a discharging current on BAT regardless the battery OVP status
5 EN_CHG R/W 1h Reset by:
WATCHDOG
REG_RST
 Charger Enable Configuration
Type : RW
POR: 1b

0h = Charge Disable

1h = Charge Enable (default)
4 EN_ICO R/W 0h Reset by:
REG_RST
 Input Current Optimizer (ICO) Enable
Type : RW
POR: 0b

0h = Disable ICO (default)

1h = Enable ICO
3 FORCE_ICO R/W 0h Reset by:
WATCHDOG
REG_RST
 Force start input current optimizer (ICO)
Note: This bit can only be set and returns 0 after ICO starts. This bit only valid when EN_ICO = 1
Type : RW
POR: 0b

0h = Do NOT force ICO (Default)

1h = Force ICO start
2 EN_HIZ R/W 0h Reset by:
REG_RST
 Enable HIZ mode.
This bit will be also reset to 0, when the adapter is plugged in at VBUS.
Type : RW
POR: 0b

0h = Disable (default)

1h = Enable
1 EN_TERM R/W 1h Reset by:
WATCHDOG
REG_RST
 Enable termination
Type : RW
POR: 1b

0h = Disable

1h = Enable (default)
0 EN_BACKUP R/W 0h Reset by:
WATCHDOG
REG_RST
 Enables backup mode where OTG automatically engages when VBUS droops below voltage set in REG10.
Type: RW
POR: 0b

0h = Disable (default)

1h = Enable

9.5.1.13 REG10_Charger_Control_1 Register (Offset = 10h) [reset = 85h]

REG10_Charger_Control_1 is shown in Figure 9-38 and described in Table 9-26.

Return to the Summary Table.

Charger Control 1

Figure 9-38 REG10_Charger_Control_1 Register
7 6 5 4 3 2 1 0
VBUS_BACKUP_1:0 VAC_OVP_1:0 WD_RST WATCHDOG_2:0
R/W-2h R/W-3h R/W-0h R/W-5h
Table 9-26 REG10_Charger_Control_1 Register Field Descriptions
Bit Field Type Reset Notes Description
7-6 VBUS_BACKUP_1:0 R/W 2h Reset by:
REG_RST
 The thresholds to trigger the backup mode, defined as a ratio of VINDPM
Type : RW
POR: 10b

0h = 40%*VINDPM

1h = 60%*VINDPM

2h = 80%*VINDPM (default)

3h = 100%*VINDPM
5-4 VAC_OVP_1:0 R/W 3h Reset by:
REG_RST
 VAC_OVP thresholds
Type : RW
POR: 11b

0h = 26V

1h = 22V

2h = 12V

3h = 7V (default)
3 WD_RST R/W 0h Reset by:
WATCHDOG
REG_RST
 I2C watch dog timer reset
Type : RW
POR: 0b

0h = Normal (default)

1h = Reset (this bit goes back to 0 after timer resets)
2-0 WATCHDOG_2:0 R/W 5h Reset by:
REG_RST
 Watchdog timer settings
Type : RW
POR: 101b

0h = Disable

1h = 0.5s

2h = 1s

3h = 2s

4h = 20s

5h = 40s (default)

6h = 80s

7h = 160s

9.5.1.14 REG11_Charger_Control_2 Register (Offset = 11h) [reset = 40h]

REG11_Charger_Control_2 is shown in Figure 9-39 and described in Table 9-27.

Return to the Summary Table.

Charger Control 2

Figure 9-39 REG11_Charger_Control_2 Register
7 6 5 4 3 2 1 0
FORCE_INDET AUTO_INDET_EN EN_12V EN_9V HVDCP_EN SDRV_CTRL_1:0 SDRV_DLY
R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 9-27 REG11_Charger_Control_2 Register Field Descriptions
Bit Field Type Reset Notes Description
7 FORCE_INDET R/W 0h Reset by:
WATCHDOG
REG_RST
 Force D+/D- detection
Type : RW
POR: 0b

0h = Do NOT force D+/D- detection (default)

1h = Force D+/D- algorithm, when D+/D- detection is done, this bit will be reset to 0
6 AUTO_INDET_EN R/W 1h Reset by:
WATCHDOG
REG_RST
 Automatic D+/D- Detection Enable
Type : RW
POR: 1b

0h = Disable D+/D- detection when VBUS is plugged-in

1h = Enable D+/D- detection when VBUS is plugged-in (default)
5 EN_12V R/W 0h Reset by:
REG_RST
 EN_12V HVDC
Type : RW
POR: 0b

0h = Disable 12V mode in HVDCP (default)

1h = Enable 12V mode in HVDCP
4 EN_9V R/W 0h Reset by:
REG_RST
 EN_9V HVDC
Type : RW
POR: 0b

0h = Disable 9V mode in HVDCP (default)

1h = Enable 9V mode in HVDCP
3 HVDCP_EN R/W 0h Reset by:
REG_RST
 High voltage DCP enable.
Type : RW
POR: 0b

0h = Disable HVDCP handshake (default)

1h = Enable HVDCP handshake
2-1 SDRV_CTRL_1:0 R/W 0h Reset by:
REG_RST
 SFET control
The external ship FET control logic to force the device enter different modes.
Type : RW
POR: 00b

0h = IDLE (default)

1h = Shutdown Mode

2h = Ship Mode

3h = System Power Reset
0 SDRV_DLY R/W 0h Reset by:
REG_RST
 Delay time added to the taking action in bit [2:1] of the SFET control
Type : RW
POR: 0b

0h = Add 10s delay time (default)

1h = Do NOT add 10s delay time

9.5.1.15 REG12_Charger_Control_3 Register (Offset = 12h) [reset = 0h]

REG12_Charger_Control_3 is shown in Figure 9-40 and described in Table 9-28.

Return to the Summary Table.

Charger Control 3

Figure 9-40 REG12_Charger_Control_3 Register
7 6 5 4 3 2 1 0
DIS_ACDRV EN_OTG PFM_OTG_DIS PFM_FWD_DIS WKUP_DLY DIS_LDO DIS_OTG_OOA DIS_FWD_OOA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 9-28 REG12_Charger_Control_3 Register Field Descriptions
Bit Field Type Reset Notes Description
7 DIS_ACDRV R/W 0h When this bit is set, the charger will force both EN_ACDRV1=0 and EN_ACDRV2=0
Type : RW
POR: 0b
6 EN_OTG R/W 0h Reset by:
WATCHDOG
REG_RST
 OTG mode control
Type : RW
POR: 0b

0h = OTG Disable (default)

1h = OTG Enable
5 PFM_OTG_DIS R/W 0h Reset by:
WATCHDOG
REG_RST
 Disable PFM in OTG mode
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
4 PFM_FWD_DIS R/W 0h Reset by:
REG_RST
 Disable PFM in forward mode
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
3 WKUP_DLY R/W 0h Reset by:
REG_RST
 When wake up the device from ship mode, how much time (tSM_EXIT) is required to pull low the QON pin.
Type : RW
POR: 0b

0h = 1s (Default)

1h = 15ms
2 DIS_LDO R/W 0h Reset by:
WATCHDOG
REG_RST
 Disable BATFET LDO mode in pre-charge stage.
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
1 DIS_OTG_OOA R/W 0h Reset by:
WATCHDOG
REG_RST
 Disable OOA in OTG mode
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
0 DIS_FWD_OOA R/W 0h Reset by:
REG_RST
 Disable OOA in forward mode
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable

9.5.1.16 REG13_Charger_Control_4 Register (Offset = 13h) [reset = X]

REG13_Charger_Control_4 is shown in Figure 9-41 and described in Table 9-29.

Return to the Summary Table.

Charger Control 4

Figure 9-41 REG13_Charger_Control_4 Register
7 6 5 4 3 2 1 0
EN_ACDRV2 EN_ACDRV1 PWM_FREQ DIS_STAT DIS_VSYS_SHORT DIS_VOTG_UVP FORCE_VINDPM_DET EN_IBUS_OCP
R/W-0h R/W-0h R/W-X R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h
Table 9-29 REG13_Charger_Control_4 Register Field Descriptions
Bit Field Type Reset Notes Description
7 EN_ACDRV2 R/W 0h External ACFET2-RBFET2 gate driver control
At POR, if the charger detects that there is no ACFET2-RBFET2 populated, this bit will be locked at 0
Type : RW
POR: 0b

0h = turn off (default)

1h = turn on
6 EN_ACDRV1 R/W 0h External ACFET1-RBFET1 gate driver control
At POR, if the charger detects that there is no ACFET1-RBFET1 populated, this bit will be locked at 0
Type : RW
POR: 0b

0h = turn off (default)

1h = turn on
5 PWM_FREQ R/W X Switching frequency selection, this bit POR default value is based on the PROG pin strapping.
Type : RW

0h = 1.5 MHz

1h = 750 kHz
4 DIS_STAT R/W 0h Reset by:
WATCHDOG
REG_RST
 Disable the STAT pin output
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
3 DIS_VSYS_SHORT R/W 0h Reset by:
REG_RST
 Disable forward mode VSYS short hiccup protection.
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
2 DIS_VOTG_UVP R/W 0h Reset by:
REG_RST
 Disable OTG mode VOTG UVP hiccup protection.
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
1 FORCE_VINDPM_DET R/W 0h Reset by:
REG_RST
 Force VINDPM detection
Note: only when VBAT>VSYSMIN, this bit can be set to 1. Once the VINDPM auto detection is done, this bits returns to 0.
Type : RW
POR: 0b

0h = Do NOT force VINDPM detection (default)

1h = Force the converter stop switching, and ADC measures the VBUS voltage without input current, then the charger updates the VINDPM register accordingly.
0 EN_IBUS_OCP R/W 1h Reset by:
REG_RST
 Enable IBUS_OCP in forward mode
Type : RW
POR: 1b

0h = Disable

1h = Enable (default)

9.5.1.17 REG14_Charger_Control_5 Register (Offset = 14h) [reset = 16h]

REG14_Charger_Control_5 is shown in Figure 9-42 and described in Table 9-30.

Return to the Summary Table.

Charger Control 5

Figure 9-42 REG14_Charger_Control_5 Register
7 6 5 4 3 2 1 0
SFET_PRESENT RESERVED EN_IBAT IBAT_REG_1:0 EN_IINDPM EN_EXTILIM EN_BATOC
R/W-0h R-0h R/W-0h R/W-2h R/W-1h R/W-1h R/W-0h
Table 9-30 REG14_Charger_Control_5 Register Field Descriptions
Bit Field Type Reset Notes Description
7 SFET_PRESENT R/W 0h The user has to set this bit based on whether a ship FET is populated or not. The POR default value is 0, which means the charger does not support all the features associated with the ship FET. The register bits list below all are locked at 0.
EN_BATOC=0

SDRV_CTRL=00
When this bit is set to 1, the register bits list above become programmable, and the charger can support the features associated with the ship FET
Type : RW
POR: 0b

0h = No ship FET populated

1h = Ship FET populated
6 RESERVED R 0h Reserved
5 EN_IBAT R/W 0h Reset by:
WATCHDOG
REG_RST
 IBAT discharge current sensing enable
Type : RW
POR: 0b

0h = Disable the IBAT discharge sensing at battery only or OTG condition (default)

1h = Enable the IBAT discharge sensing at battery only or OTG condition
4-3 IBAT_REG_1:0 R/W 2h Reset by:
WATCHDOG
REG_RST
 Battery discharging current regulation in OTG mode
Type : RW
POR: 10b

0h = 3A

1h = 4A

2h = 5A

3h = Disable (default)
2 EN_IINDPM R/W 1h Reset by:
WATCHDOG
REG_RST
 Enable the internal IINDPM register input current regulation
Type : RW
POR: 1b

0h = Disable

1h = Enable (default)
1 EN_EXTILIM R/W 1h Reset by:
REG_RST
 Enable the external ILIM_HIZ pin input current regulation
Type : RW
POR: 1b

0h = Disable

1h = Enable (default)
0 EN_BATOC R/W 0h Reset by:
WATCHDOG
REG_RST
 Enable the battery discharging current OCP
Type : RW
POR: 0b

0h = Disable (default)

1h = Enable

9.5.1.18 REG15_MPPT_Control Register (Offset = 15h) [reset = AAh]

REG15_MPPT_Control is shown in Figure 9-43 and described in Table 9-31.

Return to the Summary Table.

MPPT Control

Figure 9-43 REG15_MPPT_Control Register
7 6 5 4 3 2 1 0
VOC_PCT_2:0 VOC_DLY_1:0 VOC_RATE_1:0 EN_MPPT
R/W-5h R/W-1h R/W-1h R/W-0h
Table 9-31 REG15_MPPT_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7-5 VOC_PCT_2:0 R/W 5h Reset by:
REG_RST
 To set the VINDPM as a percentage of the VBUS open circuit voltage when the VOC measurement is done.
Type : RW
POR: 101b

0h = 0.5625

1h = 0.625

2h = 0.6875

3h = 0.75

4h = 0.8125

5h = 0.875 (default)

6h = 0.9375

7h = 1
4-3 VOC_DLY_1:0 R/W 1h Reset by:
REG_RST
 After the converter stops switching, the time delay before the VOC is measured.
Type : RW
POR: 01b

0h = 50ms

1h = 300ms (default)

2h = 2s

3h = 5s
2-1 VOC_RATE_1:0 R/W 1h Reset by:
REG_RST
 The time interval two VBUS open circuit voltage measurements.
Type : RW
POR: 01b

0h = 30s

1h = 2mins (default)

2h = 10mins

3h = 30mins
0 EN_MPPT R/W 0h Reset by:
REG_RST
 Enable the MPPT to measure the VBUS open circuit voltage.
Type : RW
POR: 0b

0h = Disable (default)

1h = Enable

9.5.1.19 REG16_Temperature_Control Register (Offset = 16h) [reset = C0h]

REG16_Temperature_Control is shown in Figure 9-44 and described in Table 9-32.

Return to the Summary Table.

Temperature Control

Figure 9-44 REG16_Temperature_Control Register
7 6 5 4 3 2 1 0
TREG_1:0 TSHUT_1:0 VBUS_PD_EN VAC1_PD_EN VAC2_PD_EN BKUP_ACFET1_ON
R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 9-32 REG16_Temperature_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7-6 TREG_1:0 R/W 3h Reset by:
WATCHDOG
REG_RST
 Thermal regulation thresholds.
Type : RW
POR: 11b

0h = 60°C

1h = 80°C

2h = 100°C

3h = 120°C (default)
5-4 TSHUT_1:0 R/W 0h Reset by:
WATCHDOG
REG_RST
 Thermal shutdown thresholds.
Type : RW
POR: 00b

0h = 150°C (default)

1h = 130°C

2h = 120°C

3h = 85°C
3 VBUS_PD_EN R/W 0h Reset by:
REG_RST
 Enable VBUS pull down resistor (6k Ohm)
Type : RW
POR: 0b

0h = Disable (default)

1h = Enable
2 VAC1_PD_EN R/W 0h Reset by:
REG_RST
 Enable VAC1 pull down resistor
Type : RW
POR: 0b

0h = Disable (default)

1h = Enable
1 VAC2_PD_EN R/W 0h Reset by:
REG_RST
 Enable VAC2 pull down resistor
Type : RW
POR: 0b

0h = Disable (default)

1h = Enable
0 BKUP_ACFET1_ON R/W 0h Reset by:
REG_RST

When the charger is operated in backup mode, ACFET1 is off. Setting this bit to 1, the charger clears the EN_BACKUP bit to 0, sets DIS_ACDRV=0 and EN_ACDRV1=1 to turn on the ACFET1.

Type: RW

POR: 0b

0h = IDLE (default)

1h = To turn on ACFET1 in backup mode

9.5.1.20 REG17_NTC_Control_0 Register (Offset = 17h) [reset = 7Ah]

REG17_NTC_Control_0 is shown in Figure 9-45 and described in Table 9-33.

Return to the Summary Table.

NTC Control 0

Figure 9-45 REG17_NTC_Control_0 Register
7 6 5 4 3 2 1 0
JEITA_VSET_2:0 JEITA_ISETH_1:0 JEITA_ISETC_1:0 RESERVED
R/W-3h R/W-3h R/W-1h R-0h
Table 9-33 REG17_NTC_Control_0 Register Field Descriptions
Bit Field Type Reset Notes Description
7-5 JEITA_VSET_2:0 R/W 3h Reset by:
WATCHDOG
REG_RST
 JEITA high temperature range (TWARN – THOT) charge voltage setting
Type : RW
POR: 011b

0h = Charge Suspend

1h = Set VREG to VREG-800mV

2h = Set VREG to VREG-600mV

3h = Set VREG to VREG-400mV (default)

4h = Set VREG to VREG-300mV

5h = Set VREG to VREG-200mV

6h = Set VREG to VREG-100mV

7h = VREG unchanged
4-3 JEITA_ISETH_1:0 R/W 3h Reset by:
WATCHDOG
REG_RST
 JEITA high temperature range (TWARN – THOT) charge current setting
Type : RW
POR: 11b

0h = Charge Suspend

1h = Set ICHG to 20%* ICHG

2h = Set ICHG to 40%* ICHG

3h = ICHG unchanged (default)
2-1 JEITA_ISETC_1:0 R/W 1h Reset by:
WATCHDOG
REG_RST
 JEITA low temperature range (TCOLD – TCOOL) charge current setting
Type : RW
POR: 01b

0h = Charge Suspend

1h = Set ICHG to 20%* ICHG (default)

2h = Set ICHG to 40%* ICHG

3h = ICHG unchanged
0 RESERVED R 0h Reserved

9.5.1.21 REG18_NTC_Control_1 Register (Offset = 18h) [reset = 54h]

REG18_NTC_Control_1 is shown in Figure 9-46 and described in Table 9-34.

Return to the Summary Table.

NTC Control 1

Figure 9-46 REG18_NTC_Control_1 Register
7 6 5 4 3 2 1 0
TS_COOL_1:0 TS_WARM_1:0 BHOT_1:0 BCOLD TS_IGNORE
R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h
Table 9-34 REG18_NTC_Control_1 Register Field Descriptions
Bit Field Type Reset Notes Description
7-6 TS_COOL_1:0 R/W 1h Reset by:
WATCHDOG
REG_RST
 JEITA VT2 comparator voltage rising thresholds as a percentage of REGN. The corresponding temperature in the brackets is achieved when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ.
Type : RW
POR: 01b

0h = 71.1% (5°C)

1h = 68.4% (default) (10°C)

2h = 65.5% (15°C)

3h = 62.4% (20°C)
5-4 TS_WARM_1:0 R/W 1h Reset by:
WATCHDOG
REG_RST
 JEITA VT3 comparator voltage falling thresholds as a percentage of REGN. The corresponding temperature in the brackets is achieved when a 103AT NTC thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ.
Type : RW
POR: 01b

0h = 48.4% (40°C)

1h = 44.8% (default) (45°C)

2h = 41.2% (50°C)

3h = 37.7% (55°C)
3-2 BHOT_1:0 R/W 1h Reset by:
WATCHDOG
REG_RST
 OTG mode TS HOT temperature threshold
Type : RW
POR: 01b

0h = 55°C

1h = 60°C (default)

2h = 65°C

3h = Disable
1 BCOLD R/W 0h Reset by:
WATCHDOG
REG_RST
 OTG mode TS COLD temperature threshold
Type : RW
POR: 0b

0h = -10°C (default)

1h = -20°C
0 TS_IGNORE R/W 0h Reset by:
WATCHDOG
REG_RST
 Ignore the TS feedback, the charger considers the TS is always good to allow the charging and OTG modes, all the four TS status bits always stay at 0000 to report the normal condition.
Type : RW
POR: 0b

0h = NOT ignore (Default)

1h = Ignore

9.5.1.22 REG19_ICO_Current_Limit Register (Offset = 19h) [reset = 0h]

REG19_ICO_Current_Limit is shown in Figure 9-47 and described in Table 9-35.

Return to the Summary Table.

ICO Current Limit

Figure 9-47 REG19_ICO_Current_Limit Register
15 14 13 12 11 10 9 8
RESERVED ICO_ILIM_8:0
R-0h R-0h
7 6 5 4 3 2 1 0
ICO_ILIM_8:0
R-0h
Table 9-35 REG19_ICO_Current_Limit Register Field Descriptions
Bit Field Type Reset Description
15-9 RESERVED R 0h

RESERVED
8-0 ICO_ILIM_8:0 R 0h

Input Current Limit obtained from ICO or ILIM_HIZ pin setting
Type : R
POR: 0mA (0h)
Range : 100mA-3300mA
Fixed Offset : 0mA
Bit Step Size : 10mA
Clamped Low

9.5.1.23 REG1B_Charger_Status_0 Register (Offset = 1Bh) [reset = 0h]

REG1B_Charger_Status_0 is shown in Figure 9-48 and described in Table 9-36.

Return to the Summary Table.

Charger Status 0

Figure 9-48 REG1B_Charger_Status_0 Register
7 6 5 4 3 2 1 0
IINDPM_STAT VINDPM_STAT WD_STAT RESERVED PG_STAT AC2_PRESENT_STAT AC1_PRESENT_STAT VBUS_PRESENT_STAT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-36 REG1B_Charger_Status_0 Register Field Descriptions
Bit Field Type Reset Description
7 IINDPM_STAT R 0h

IINDPM status (forward mode) or IOTG status (OTG mode)
Type : R
POR: 0b

0h = Normal

1h = In IINDPM regulation or IOTG regulation
6 VINDPM_STAT R 0h

VINDPM status (forward mode) or VOTG status (OTG mode)
Type : R
POR: 0b

0h = Normal

1h = In VINDPM regulation or VOTG regualtion
5 WD_STAT R 0h

I2C watch dog timer status
Type : R
POR: 0b

0h = Normal

1h = WD timer expired
4 RESERVED R 0h RESERVED
3 PG_STAT R 0h

Power Good Status
Type : R
POR: 0b

0h = NOT in power good status

1h = Power good
2 AC2_PRESENT_STAT R 0h

VAC2 insert status
Type : R
POR: 0b

0h = VAC2 NOT present

1h = VAC2 present (above present threshold)
1 AC1_PRESENT_STAT R 0h

VAC1 insert status
Type : R
POR: 0b

0h = VAC1 NOT present

1h = VAC1 present (above present threshold)
0 VBUS_PRESENT_STAT R 0h

VBUS present status
Type : R
POR: 0b

0h = VBUS NOT present

1h = VBUS present (above present threshold)

9.5.1.24 REG1C_Charger_Status_1 Register (Offset = 1Ch) [reset = 0h]

REG1C_Charger_Status_1 is shown in Figure 9-49 and described in Table 9-37.

Return to the Summary Table.

Charger Status 1

Figure 9-49 REG1C_Charger_Status_1 Register
7 6 5 4 3 2 1 0
CHG_STAT_2:0 VBUS_STAT_3:0 BC1.2_DONE_STAT
R-0h R-0h R-0h
Table 9-37 REG1C_Charger_Status_1 Register Field Descriptions
Bit Field Type Reset Description
7-5 CHG_STAT_2:0 R 0h

Charge Status bits
Type : R
POR: 000b

0h = Not Charging

1h = Trickle Charge

2h = Pre-charge

3h = Fast charge (CC mode)

4h = Taper Charge (CV mode)

5h = Reserved

6h = Top-off Timer Active Charging

7h = Charge Termination Done
4-1 VBUS_STAT_3:0 R 0h

VBUS status bits
0h: No Input or BHOT or BCOLD in OTG mode
1h: USB SDP (500mA)
2h: USB CDP (1.5A)
3h: USB DCP (3.25A)
4h: Adjustable High Voltage DCP (HVDCP) (1.5A)
5h: Unknown adaptor (3A)
6h: Non-Standard Adapter (1A/2A/2.1A/2.4A)
7h: In OTG mode
8h: Not qualified adaptor
9h: Reserved
Ah: Reserved
Bh: Device directly powered from VBUS
Ch: Backup Mode
Dh: Reserved
Eh: Reserved
Fh: Reserved
Type : R
POR: 0h
0 BC1.2_DONE_STAT R 0h

BC1.2 status bit
Type : R
POR: 0b

0h = BC1.2 or non-standard detection NOT complete

1h = BC1.2 or non-standard detection complete

9.5.1.25 REG1D_Charger_Status_2 Register (Offset = 1Dh) [reset = 0h]

REG1D_Charger_Status_2 is shown in Figure 9-50 and described in Table 9-38.

Return to the Summary Table.

Charger Status 2

Figure 9-50 REG1D_Charger_Status_2 Register
7 6 5 4 3 2 1 0
ICO_STAT_1:0 RESERVED TREG_STAT DPDM_STAT VBAT_PRESENT_STAT
R-0h R-0h R-0h R-0h R-0h
Table 9-38 REG1D_Charger_Status_2 Register Field Descriptions
Bit Field Type Reset Description
7-6 ICO_STAT_1:0 R 0h

Input Current Optimizer (ICO) status
Type : R
POR: 00b

0h = ICO disabled

1h = ICO optimization in progress

2h = Maximum input current detected

3h = Reserved
5-3 RESERVED R 0h

RESERVED
2 TREG_STAT R 0h

IC thermal regulation status
Type : R
POR: 0b

0h = Normal

1h = Device in thermal regulation
1 DPDM_STAT R 0h

D+/D- detection status bits
Type : R
POR: 0b

0h = The D+/D- detection is NOT started yet, or the detection is done

1h = The D+/D- detection is ongoing
0 VBAT_PRESENT_STAT R 0h

Battery present status (VBAT > VBAT_UVLOZ)
Type : R
POR: 0b

0h = VBAT NOT present

1h = VBAT present

9.5.1.26 REG1E_Charger_Status_3 Register (Offset = 1Eh) [reset = 0h]

REG1E_Charger_Status_3 is shown in Figure 9-51 and described in Table 9-39.

Return to the Summary Table.

Charger Status 3

Figure 9-51 REG1E_Charger_Status_3 Register
7 6 5 4 3 2 1 0
ACRB2_STAT ACRB1_STAT ADC_DONE_STAT VSYS_STAT CHG_TMR_STAT TRICHG_TMR_STAT PRECHG_TMR_STAT RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-39 REG1E_Charger_Status_3 Register Field Descriptions
Bit Field Type Reset Description
7 ACRB2_STAT R 0h

The ACFET2-RBFET2 status
Type : R
POR: 0b

0h = ACFET2-RBFET2 is NOT placed

1h = ACFET2-RBFET2 is placed
6 ACRB1_STAT R 0h

The ACFET1-RBFET1 status
Type : R
POR: 0b

0h = ACFET1-RBFET1 is NOT placed

1h = ACFET1-RBFET1 is placed
5 ADC_DONE_STAT R 0h

ADC Conversion Status (in one-shot mode only)
Type : R
POR: 0b

0h = Conversion NOT complete

1h = Conversion complete
4 VSYS_STAT R 0h

VSYS Regulation Status (forward mode)
Type : R
POR: 0b

0h = Not in VSYSMIN regulation (VBAT > VSYSMIN)

1h = In VSYSMIN regulation (VBAT < VSYSMIN)
3 CHG_TMR_STAT R 0h

Fast charge timer status
Type : R
POR: 0b

0h = Normal

1h = Safety timer expired
2 TRICHG_TMR_STAT R 0h

Trickle charge timer status
Type : R
POR: 0b

0h = Normal

1h = Safety timer expired
1 PRECHG_TMR_STAT R 0h

Pre-charge timer status
Type : R
POR: 0b

0h = Normal

1h = Safety timer expired
0 RESERVED R 0h

RESERVED

9.5.1.27 REG1F_Charger_Status_4 Register (Offset = 1Fh) [reset = 0h]

REG1F_Charger_Status_4 is shown in Figure 9-52 and described in Table 9-40.

Return to the Summary Table.

Charger Status 4

Figure 9-52 REG1F_Charger_Status_4 Register
7 6 5 4 3 2 1 0
RESERVED VBATOTG_LOW_STAT TS_COLD_STAT TS_COOL_STAT TS_WARM_STAT TS_HOT_STAT
R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-40 REG1F_Charger_Status_4 Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 0h

RESERVED
4 VBATOTG_LOW_STAT R 0h

The battery voltage is too low to enable OTG mode.
Type : R
POR: 0b

0h = The battery voltage is high enough to enable the OTG operation

1h = The battery volage is too low to enable the OTG operation
3 TS_COLD_STAT R 0h

The TS temperature is in the cold range, lower than T1.
Type : R
POR: 0b

0h = TS status is NOT in cold range

1h = TS status is in cold range
2 TS_COOL_STAT R 0h

The TS temperature is in the cool range, between T1 and T2.
Type : R
POR: 0b

0h = TS status is NOT in cool range

1h = TS status is in cool range
1 TS_WARM_STAT R 0h

The TS temperature is in the warm range, between T3 and T5.
Type : R
POR: 0b

0h = TS status is NOT in warm range

1h = TS status is in warm range
0 TS_HOT_STAT R 0h

The TS temperature is in the hot range, higher than T5.
Type : R
POR: 0b

0h = TS status is NOT in hot range

1h = TS status is in hot range

9.5.1.28 REG20_FAULT_Status_0 Register (Offset = 20h) [reset = 0h]

REG20_FAULT_Status_0 is shown in Figure 9-53 and described in Table 9-41.

Return to the Summary Table.

FAULT Status 0

Figure 9-53 REG20_FAULT_Status_0 Register
7 6 5 4 3 2 1 0
IBAT_REG_STAT VBUS_OVP_STAT VBAT_OVP_STAT IBUS_OCP_STAT IBAT_OCP_STAT CONV_OCP_STAT VAC2_OVP_STAT VAC1_OVP_STAT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-41 REG20_FAULT_Status_0 Register Field Descriptions
Bit Field Type Reset Description
7 IBAT_REG_STAT R 0h

IBAT regulation status
Type : R
POR: 0b

0h = Normal

1h = Device in battery discharging current regulation
6 VBUS_OVP_STAT R 0h

VBUS over-voltage status
Type : R
POR: 0b

0h = Normal

1h = Device in over voltage protection
5 VBAT_OVP_STAT R 0h

VBAT over-voltage status
Type : R
POR: 0b

0h = Normal

1h = Device in over voltage protection
4 IBUS_OCP_STAT R 0h

IBUS over-current status
Type : R
POR: 0b

0h = Normal

1h = Device in over current protection
3 IBAT_OCP_STAT R 0h

IBAT over-current status
Type : R
POR: 0b

0h = Normal

1h = Device in over current protection
2 CONV_OCP_STAT R 0h

Converter over current status
Type : R
POR: 0b

0h = Normal

1h = Converter in over current protection
1 VAC2_OVP_STAT R 0h

VAC2 over-voltage status
Type : R
POR: 0b

0h = Normal

1h = Device in over voltage protection
0 VAC1_OVP_STAT R 0h

VAC1 over-voltage status
Type : R
POR: 0b

0h = Normal

1h = Device in over voltage protection

9.5.1.29 REG21_FAULT_Status_1 Register (Offset = 21h) [reset = 0h]

REG21_FAULT_Status_1 is shown in Figure 9-54 and described in Table 9-42.

Return to the Summary Table.

FAULT Status 1

Figure 9-54 REG21_FAULT_Status_1 Register
7 6 5 4 3 2 1 0
VSYS_SHORT_STAT VSYS_OVP_STAT OTG_OVP_STAT OTG_UVP_STAT RESERVED TSHUT_STAT RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-42 REG21_FAULT_Status_1 Register Field Descriptions
Bit Field Type Reset Description
7 VSYS_SHORT_STAT R 0h

VSYS short circuit status
Type : R
POR: 0b

0h = Normal

1h = Device in SYS short circuit protection
6 VSYS_OVP_STAT R 0h

VSYS over-voltage status
Type : R
POR: 0b

0h = Normal

1h = Device in SYS over-voltage protection
5 OTG_OVP_STAT R 0h

OTG over voltage status
Type : R
POR: 0b

0h = Normal

1h = Device in OTG over-voltage
4 OTG_UVP_STAT R 0h

OTG under voltage status.
Type : R
POR: 0b

0h = Normal

1h = Device in OTG under voltage
3 RESERVED R 0h

RESERVED
2 TSHUT_STAT R 0h

IC temperature shutdown status
Type : R
POR: 0b

0h = Normal

1h = Device in thermal shutdown protection
1-0 RESERVED R 0h

RESERVED

9.5.1.30 REG22_Charger_Flag_0 Register (Offset = 22h) [reset = 0h]

REG22_Charger_Flag_0 is shown in Figure 9-55 and described in Table 9-43.

Return to the Summary Table.

Charger Flag 0

Figure 9-55 REG22_Charger_Flag_0 Register
7 6 5 4 3 2 1 0
IINDPM_FLAG VINDPM_FLAG WD_FLAG POORSRC_FLAG PG_FLAG AC2_PRESENT_FLAG AC1_PRESENT_FLAG VBUS_PRESENT_FLAG
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-43 REG22_Charger_Flag_0 Register Field Descriptions
Bit Field Type Reset Description
7 IINDPM_FLAG R 0h

IINDPM / IOTG flag
Type : R
POR: 0b

0h = Normal

1h = IINDPM / IOTG signal rising edge detected
6 VINDPM_FLAG R 0h

VINDPM / VOTG Flag
Type : R
POR: 0b

0h = Normal

1h = VINDPM / VOTG regulation signal rising edge detected
5 WD_FLAG R 0h

I2C watchdog timer flag
Type : R
POR: 0b

0h = Normal

1h = WD timer signal rising edge detected
4 POORSRC_FLAG R 0h

Poor source detection flag
Type : R
POR: 0b

0h = Normal

1h = Poor source status rising edge detected
3 PG_FLAG R 0h

Power good flag
Type : R
POR: 0b

0h = Normal

1h = Any change in PG_STAT even (adapter good qualification or adapter good going away)
2 AC2_PRESENT_FLAG R 0h

VAC2 present flag
Type : R
POR: 0b

0h = Normal

1h = VAC2 present status changed
1 AC1_PRESENT_FLAG R 0h

VAC1 present flag
Type : R
POR: 0b

0h = Normal

1h = VAC1 present status changed
0 VBUS_PRESENT_FLAG R 0h

VBUS present flag
Type : R
POR: 0b

0h = Normal

1h = VBUS present status changed

9.5.1.31 REG23_Charger_Flag_1 Register (Offset = 23h) [reset = 0h]

REG23_Charger_Flag_1 is shown in Figure 9-56 and described in Table 9-44.

Return to the Summary Table.

Charger Flag 1

Figure 9-56 REG23_Charger_Flag_1 Register
7 6 5 4 3 2 1 0
CHG_FLAG ICO_FLAG RESERVED VBUS_FLAG RESERVED TREG_FLAG VBAT_PRESENT_FLAG BC1.2_DONE_FLAG
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-44 REG23_Charger_Flag_1 Register Field Descriptions
Bit Field Type Reset Description
7 CHG_FLAG R 0h

Charge status flag
Type : R
POR: 0b

0h = Normal

1h = Charge status changed
6 ICO_FLAG R 0h

ICO status flag
Type : R
POR: 0b

0h = Normal

1h = ICO status changed
5 RESERVED R 0h

RESERVED
4 VBUS_FLAG R 0h

VBUS status flag
Type : R
POR: 0b

0h = Normal

1h = VBUS status changed
3 RESERVED R 0h

RESERVED
2 TREG_FLAG R 0h

IC thermal regulation flag
Type : R
POR: 0b

0h = Normal

1h = TREG signal rising threshold detected
1 VBAT_PRESENT_FLAG R 0h

VBAT present flag
Type : R
POR: 0b

0h = Normal

1h = VBAT present status changed
0 BC1.2_DONE_FLAG R 0h

BC1.2 status Flag
Type : R
POR: 0b

0h = Normal

1h = BC1.2 detection status changed

9.5.1.32 REG24_Charger_Flag_2 Register (Offset = 24h) [reset = 0h]

REG24_Charger_Flag_2 is shown in Figure 9-57 and described in Table 9-45.

Return to the Summary Table.

Charger Flag 2

Figure 9-57 REG24_Charger_Flag_2 Register
7 6 5 4 3 2 1 0
RESERVED DPDM_DONE_FLAG ADC_DONE_FLAG VSYS_FLAG CHG_TMR_FLAG TRICHG_TMR_FLAG PRECHG_TMR_FLAG TOPOFF_TMR_FLAG
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-45 REG24_Charger_Flag_2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0h

RESERVED
6 DPDM_DONE_FLAG R 0h

D+/D- detection is done flag.
Type : R
POR: 0b

0h = D+/D- detection is NOT started or still ongoing

1h = D+/D- detection is completed
5 ADC_DONE_FLAG R 0h

ADC conversion flag (only in one-shot mode)
Type : R
POR: 0b

0h = Conversion NOT completed

1h = Conversion completed
4 VSYS_FLAG R 0h

VSYSMIN regulation flag
Type : R
POR: 0b

0h = Normal

1h = Entered or existed VSYSMIN regulation
3 CHG_TMR_FLAG R 0h

Fast charge timer flag
Type : R
POR: 0b

0h = Normal

1h = Fast charge timer expired rising edge detected
2 TRICHG_TMR_FLAG R 0h

Trickle charge timer flag
Type : R
POR: 0b

0h = Normal

1h = Trickle charger timer expired rising edge detected
1 PRECHG_TMR_FLAG R 0h

Pre-charge timer flag
Type : R
POR: 0b

0h = Normal

1h = Pre-charge timer expired rising edge detected
0 TOPOFF_TMR_FLAG R 0h

Top off timer flag
Type : R
POR: 0b

0h = Normal

1h = Top off timer expired rising edge detected

9.5.1.33 REG25_Charger_Flag_3 Register (Offset = 25h) [reset = 0h]

REG25_Charger_Flag_3 is shown in Figure 9-58 and described in Table 9-46.

Return to the Summary Table.

Charger Flag 3

Figure 9-58 REG25_Charger_Flag_3 Register
7 6 5 4 3 2 1 0
RESERVED VBATOTG_LOW_FLAG TS_COLD_FLAG TS_COOL_FLAG TS_WARM_FLAG TS_HOT_FLAG
R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-46 REG25_Charger_Flag_3 Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R 0h

RESERVED
4 VBATOTG_LOW_FLAG R 0h

VBAT too low to enable OTG flag
Type : R
POR: 0b

0h = Normal

1h = VBAT falls below the threshold to enable the OTG mode
3 TS_COLD_FLAG R 0h

TS cold temperature flag
Type : R
POR: 0b

0h = Normal

1h = TS across cold temperature (T1) is detected
2 TS_COOL_FLAG R 0h

TS cool temperature flag
Type : R
POR: 0b

0h = Normal

1h = TS across cool temperature (T2) is detected
1 TS_WARM_FLAG R 0h

TS warm temperature flag
Type : R
POR: 0b

0h = Normal

1h = TS across warm temperature (T3) is detected
0 TS_HOT_FLAG R 0h

TS hot temperature flag
Type : R
POR: 0b

0h = Normal

1h = TS across hot temperature (T5) is detected

9.5.1.34 REG26_FAULT_Flag_0 Register (Offset = 26h) [reset = 0h]

REG26_FAULT_Flag_0 is shown in Figure 9-59 and described in Table 9-47.

Return to the Summary Table.

FAULT Flag 0

Figure 9-59 REG26_FAULT_Flag_0 Register
7 6 5 4 3 2 1 0
IBAT_REG_FLAG VBUS_OVP_FLAG VBAT_OVP_FLAG IBUS_OCP_FLAG IBAT_OCP_FLAG CONV_OCP_FLAG VAC2_OVP_FLAG VAC1_OVP_FLAG
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-47 REG26_FAULT_Flag_0 Register Field Descriptions
Bit Field Type Reset Description
7 IBAT_REG_FLAG R 0h

IBAT regulation flag
Type : R
POR: 0b

0h = Normal

1h = Enter or exit IBAT regulation
6 VBUS_OVP_FLAG R 0h

VBUS over-voltage flag
Type : R
POR: 0b

0h = Normal

1h = Enter VBUS OVP
5 VBAT_OVP_FLAG R 0h

VBAT over-voltage flag
Type : R
POR: 0b

0h = Normal

1h = Enter VBAT OVP
4 IBUS_OCP_FLAG R 0h

IBUS over-current flag
Type : R
POR: 0b

0h = Normal

1h = Enter IBUS OCP
3 IBAT_OCP_FLAG R 0h

IBAT over-current flag
Type : R
POR: 0b

0h = Normal

1h = Enter discharged OCP
2 CONV_OCP_FLAG R 0h

Converter over-current flag
Type : R
POR: 0b

0h = Normal

1h = Enter converter OCP
1 VAC2_OVP_FLAG R 0h

VAC2 over-voltage flag
Type : R
POR: 0b

0h = Normal

1h = Enter VAC2 OVP
0 VAC1_OVP_FLAG R 0h

VAC1 over-voltage flag
Type : R
POR: 0b

0h = Normal

1h = Enter VAC1 OVP

9.5.1.35 REG27_FAULT_Flag_1 Register (Offset = 27h) [reset = 0h]

REG27_FAULT_Flag_1 is shown in Figure 9-60 and described in Table 9-48.

Return to the Summary Table.

FAULT Flag 1

Figure 9-60 REG27_FAULT_Flag_1 Register
7 6 5 4 3 2 1 0
VSYS_SHORT_FLAG VSYS_OVP_FLAG OTG_OVP_FLAG OTG_UVP_FLAG RESERVED TSHUT_FLAG RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 9-48 REG27_FAULT_Flag_1 Register Field Descriptions
Bit Field Type Reset Description
7 VSYS_SHORT_FLAG R 0h

VSYS short circuit flag
Type : R
POR: 0b

0h = Normal

1h = Stop switching due to system short
6 VSYS_OVP_FLAG R 0h

VSYS over-voltage flag
Type : R
POR: 0b

0h = Normal

1h = Stop switching due to system over-voltage
5 OTG_OVP_FLAG R 0h

OTG over-voltage flag
Type : R
POR: 0b

0h = Normal

1h = Stop OTG due to VBUS over voltage
4 OTG_UVP_FLAG R 0h

OTG under-voltage flag
Type : R
POR: 0b

0h = Normal

1h = Stop OTG due to VBUS under-voltage
3 RESERVED R 0h

RESERVED
2 TSHUT_FLAG R 0h

IC thermal shutdown flag
Type : R
POR: 0b

0h = Normal

1h = TS shutdown signal rising threshold detected
1-0 RESERVED R 0h

RESERVED

9.5.1.36 REG28_Charger_Mask_0 Register (Offset = 28h) [reset = 0h]

REG28_Charger_Mask_0 is shown in Figure 9-61 and described in Table 9-49.

Return to the Summary Table.

Charger Mask 0

Figure 9-61 REG28_Charger_Mask_0 Register
7 6 5 4 3 2 1 0
IINDPM_MASK VINDPM_MASK WD_MASK POORSRC_MASK PG_MASK AC2_PRESENT_MASK AC1_PRESENT_MASK VBUS_PRESENT_MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 9-49 REG28_Charger_Mask_0 Register Field Descriptions
Bit Field Type Reset Notes Description
7 IINDPM_MASK R/W 0h Reset by:
REG_RST
 IINDPM / IOTG mask flag
Type : RW
POR: 0b

0h = Enter IINDPM / IOTG does produce INT pulse

1h = Enter IINDPM / IOTG does NOT produce INT pulse
6 VINDPM_MASK R/W 0h Reset by:
REG_RST
 VINDPM / VOTG mask flag
Type : RW
POR: 0b

0h = Enter VINDPM / VOTG does produce INT pulse

1h = Enter VINDPM / VOTG does NOT produce INT pulse
5 WD_MASK R/W 0h Reset by:
REG_RST
 I2C watch dog timer mask flag
Type : RW
POR: 0b

0h = I2C watch dog timer expired does produce INT pulse

1h = I2C watch dog timer expired does NOT produce INT pulse
4 POORSRC_MASK R/W 0h Reset by:
REG_RST
 Poor source detection mask flag
Type : RW
POR: 0b

0h = Poor source detected does produce INT

1h = Poor source detected does NOT produce INT
3 PG_MASK R/W 0h Reset by:
REG_RST
 Power Good mask flag
Type : RW
POR: 0b

0h = PG toggle does produce INT

1h = PG toggle does NOT produce INT
2 AC2_PRESENT_MASK R/W 0h Reset by:
REG_RST
 VAC2 present mask flag
Type : RW
POR: 0b

0h = VAC2 present status change does produce INT

1h = VAC2 present status change does NOT produce INT
1 AC1_PRESENT_MASK R/W 0h Reset by:
REG_RST
 VAC1 present mask flag
Type : RW
POR: 0b

0h = VAC1 present status change does produce INT

1h = VAC1 present status change does NOT produce INT
0 VBUS_PRESENT_MASK R/W 0h Reset by:
REG_RST
 VBUS present mask flag
Type : RW
POR: 0b

0h = VBUS present status change does produce INT

1h = VBUS present status change does NOT produce INT

9.5.1.37 REG29_Charger_Mask_1 Register (Offset = 29h) [reset = 0h]

REG29_Charger_Mask_1 is shown in Figure 9-62 and described in Table 9-50.

Return to the Summary Table.

Charger Mask 1

Figure 9-62 REG29_Charger_Mask_1 Register
7 6 5 4 3 2 1 0
CHG_MASK ICO_MASK RESERVED VBUS_MASK RESERVED TREG_MASK VBAT_PRESENT_MASK BC1.2_DONE_MASK
R/W-0h R/W-0h R-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h
Table 9-50 REG29_Charger_Mask_1 Register Field Descriptions
Bit Field Type Reset Notes Description
7 CHG_MASK R/W 0h Reset by:
REG_RST
 Charge status mask flag
Type : RW
POR: 0b

0h = Charging status change does produce INT

1h = Charging status change does NOT produce INT
6 ICO_MASK R/W 0h Reset by:
REG_RST
 ICO status mask flag
Type : RW
POR: 0b

0h = ICO status change does produce INT

1h = ICO status change does NOT produce INT
5 RESERVED R 0h RESERVED
4 VBUS_MASK R/W 0h Reset by:
REG_RST
 VBUS status mask flag
Type : RW
POR: 0b

0h = VBUS status change does produce INT

1h = VBUS status change does NOT produce INT
3 RESERVED R 0h RESERVED
2 TREG_MASK R/W 0h Reset by:
REG_RST
 IC thermal regulation mask flag
Type : RW
POR: 0b

0h = entering TREG does produce INT

1h = entering TREG does NOT produce INT
1 VBAT_PRESENT_MASK R/W 0h Reset by:
REG_RST
 VBAT present mask flag
Type : RW
POR: 0b

0h = VBAT present status change does produce INT

1h = VBAT present status change does NOT produce INT
0 BC1.2_DONE_MASK R/W 0h Reset by:
REG_RST
 BC1.2 status mask flag
Type : RW
POR: 0b

0h = BC1.2 status change does produce INT

1h = BC1.2 status change does NOT produce INT

9.5.1.38 REG2A_Charger_Mask_2 Register (Offset = 2Ah) [reset = 0h]

REG2A_Charger_Mask_2 is shown in Figure 9-63 and described in Table 9-51.

Return to the Summary Table.

Charger Mask 2

Figure 9-63 REG2A_Charger_Mask_2 Register
7 6 5 4 3 2 1 0
RESERVED DPDM_DONE_MASK ADC_DONE_MASK VSYS_MASK CHG_TMR_MASK TRICHG_TMR_MASK PRECHG_TMR_MASK TOPOFF_TMR_MASK
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 9-51 REG2A_Charger_Mask_2 Register Field Descriptions
Bit Field Type Reset Notes Description
7 RESERVED R 0h RESERVED
6 DPDM_DONE_MASK R/W 0h Reset by:
REG_RST
 D+/D- detection is done mask flag
Type : RW
POR: 0b

0h = D+/D- detection done does produce INT pulse

1h = D+/D- detection done does NOT produce INT pulse
5 ADC_DONE_MASK R/W 0h Reset by:
REG_RST
 ADC conversion mask flag (only in one-shot mode)
Type : RW
POR: 0b

0h = ADC conversion done does produce INT pulse

1h = ADC conversion done does NOT produce INT pulse
4 VSYS_MASK R/W 0h Reset by:
REG_RST
 VSYS min regulation mask flag
Type : RW
POR: 0b

0h = enter or exit VSYSMIN regulation does produce INT pulse

1h = enter or exit VSYSMIN regulation does NOT produce INT pulse
3 CHG_TMR_MASK R/W 0h Reset by:
REG_RST
 Fast charge timer mask flag
Type : RW
POR: 0b

0h = Fast charge timer expire does produce INT

1h = Fast charge timer expire does NOT produce INT
2 TRICHG_TMR_MASK R/W 0h Reset by:
REG_RST
 Trickle charge timer mask flag
Type : RW
POR: 0b

0h = Trickle charge timer expire does produce INT

1h = Trickle charge timer expire does NOT produce INT
1 PRECHG_TMR_MASK R/W 0h Reset by:
REG_RST
 Pre-charge timer mask flag
Type : RW
POR: 0b

0h = Pre-charge timer expire does produce INT

1h = Pre-charge timer expire does NOT produce INT
0 TOPOFF_TMR_MASK R/W 0h Reset by:
REG_RST
 Top off timer mask flag
Type : RW
POR: 0b

0h = Top off timer expire does produce INT

1h = Top off timer expire does NOT produce INT

9.5.1.39 REG2B_Charger_Mask_3 Register (Offset = 2Bh) [reset = 0h]

REG2B_Charger_Mask_3 is shown in Figure 9-64 and described in Table 9-52.

Return to the Summary Table.

Charger Mask 3

Figure 9-64 REG2B_Charger_Mask_3 Register
7 6 5 4 3 2 1 0
RESERVED VBATOTG_LOW_MASK TS_COLD_MASK TS_COOL_MASK TS_WARM_MASK TS_HOT_MASK
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 9-52 REG2B_Charger_Mask_3 Register Field Descriptions
Bit Field Type Reset Notes Description
7-5 RESERVED R 0h RESERVED
4 VBATOTG_LOW_MASK R/W 0h Reset by:
WATCHDOG
REG_RST
 VBAT too low to enable OTG mask
Type : RW
POR: 0b

0h = VBAT falling below the threshold to enable the OTG mode, does produce INT

1h = VBAT falling below the threshold to enable the OTG mode, does NOT produce INT
3 TS_COLD_MASK R/W 0h Reset by:
WATCHDOG
REG_RST
 TS cold temperature interrupt mask
Type : RW
POR: 0b

0h = TS across cold temperature (T1) does produce INT

1h = TS across cold temperature (T1) does NOT produce INT
2 TS_COOL_MASK R/W 0h Reset by:
WATCHDOG
REG_RST
 TS cool temperature interrupt mask
Type : RW
POR: 0b

0h = TS across cool temperature (T2) does produce INT

1h = TS across cool temperature (T2) does NOT produce INT
1 TS_WARM_MASK R/W 0h Reset by:
WATCHDOG
REG_RST
 TS warm temperature interrupt mask
Type : RW
POR: 0b

0h = TS across warm temperature (T3) does produce INT

1h = TS across warm temperature (T3) does NOT produce INT
0 TS_HOT_MASK R/W 0h Reset by:
WATCHDOG
REG_RST
 TS hot temperature interrupt mask
Type : RW
POR: 0b

0h = TS across hot temperature (T5) does produce INT

1h = TS across hot temperature (T5) does NOT produce INT

9.5.1.40 REG2C_FAULT_Mask_0 Register (Offset = 2Ch) [reset = 0h]

REG2C_FAULT_Mask_0 is shown in Figure 9-65 and described in Table 9-53.

Return to the Summary Table.

FAULT Mask 0

Figure 9-65 REG2C_FAULT_Mask_0 Register
7 6 5 4 3 2 1 0
IBAT_REG_MASK VBUS_OVP_MASK VBAT_OVP_MASK IBUS_OCP_MASK IBAT_OCP_MASK CONV_OCP_MASK VAC2_OVP_MASK VAC1_OVP_MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 9-53 REG2C_FAULT_Mask_0 Register Field Descriptions
Bit Field Type Reset Notes Description
7 IBAT_REG_MASK R/W 0h Reset by:
REG_RST
 IBAT regulation mask flag
Type : RW
POR: 0b

0h = enter or exit IBAT regulation does produce INT

1h = enter or exit IBAT regulation does NOT produce INT
6 VBUS_OVP_MASK R/W 0h Reset by:
REG_RST
 VBUS over-voltage mask flag
Type : RW
POR: 0b

0h = entering VBUS OVP does produce INT

1h = entering VBUS OVP does NOT produce INT
5 VBAT_OVP_MASK R/W 0h Reset by:
REG_RST
 VBAT over-voltage mask flag
Type : RW
POR: 0b

0h = entering VBAT OVP does produce INT

1h = entering VBAT OVP does NOT produce INT
4 IBUS_OCP_MASK R/W 0h Reset by:
REG_RST
 IBUS over-current mask flag
Type : RW
POR: 0b

0h = IBUS OCP fault does produce INT

1h = IBUS OCP fault does NOT produce INT
3 IBAT_OCP_MASK R/W 0h Reset by:
REG_RST
 IBAT over-current mask flag
Type : RW
POR: 0b

0h = IBAT OCP fault does produce INT

1h = IBAT OCP fault does NOT produce INT
2 CONV_OCP_MASK R/W 0h Reset by:
REG_RST
 Converter over-current mask flag
Type : RW
POR: 0b

0h = Converter OCP fault does produce INT

1h = Converter OCP fault does NOT produce INT
1 VAC2_OVP_MASK R/W 0h Reset by:
REG_RST
 VAC2 over-voltage mask flag
Type : RW
POR: 0b

0h = entering VAC2 OVP does produce INT

1h = entering VAC2 OVP does NOT produce INT
0 VAC1_OVP_MASK R/W 0h Reset by:
REG_RST
 VAC1 over-voltage mask flag
Type : RW
POR: 0b

0h = entering VAC1 OVP does produce INT

1h = entering VAC1 OVP does NOT produce INT

9.5.1.41 REG2D_FAULT_Mask_1 Register (Offset = 2Dh) [reset = 0h]

REG2D_FAULT_Mask_1 is shown in Figure 9-66 and described in Table 9-54.

Return to the Summary Table.

FAULT Mask 1

Figure 9-66 REG2D_FAULT_Mask_1 Register
7 6 5 4 3 2 1 0
VSYS_SHORT_MASK VSYS_OVP_MASK OTG_OVP_MASK OTG_UVP_MASK RESERVED TSHUT_MASK RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h
Table 9-54 REG2D_FAULT_Mask_1 Register Field Descriptions
Bit Field Type Reset Notes Description
7 VSYS_SHORT_MASK R/W 0h Reset by:
REG_RST
 VSYS short circuit mask flag
Type : RW
POR: 0b

0h = System short fault does produce INT

1h = System short fault does NOT produce INT
6 VSYS_OVP_MASK R/W 0h Reset by:
REG_RST
 VSYS over-voltage mask flag
Type : RW
POR: 0b

0h = System over-voltage fault does produce INT

1h = System over-voltage fault does NOT produce INT
5 OTG_OVP_MASK R/W 0h Reset by:
REG_RST
 OTG over-voltage mask flag
Type : RW
POR: 0b

0h = OTG VBUS over-voltage fault does produce INT

1h = OTG VBUS over-voltage fault does NOT produce INT
4 OTG_UVP_MASK R/W 0h Reset by:
REG_RST
 OTG under-voltage mask flag
Type : RW
POR: 0b

0h = OTG VBUS under voltage fault does produce INT

1h = OTG VBUS under voltage fault does NOT produce INT
3 RESERVED R/W 0h RESERVED
2 TSHUT_MASK R/W 0h Reset by:
REG_RST
 IC thermal shutdown mask flag
Type : RW
POR: 0b

0h = TSHUT does produce INT

1h = TSHUT does NOT produce INT
1-0 RESERVED R 0h RESERVED

9.5.1.42 REG2E_ADC_Control Register (Offset = 2Eh) [reset = 30h]

REG2E_ADC_Control is shown in Figure 9-67 and described in Table 9-55.

Return to the Summary Table.

ADC Control

Figure 9-67 REG2E_ADC_Control Register
7 6 5 4 3 2 1 0
ADC_EN ADC_RATE ADC_SAMPLE_1:0 ADC_AVG ADC_AVG_INIT RESERVED
R/W-0h R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h
Table 9-55 REG2E_ADC_Control Register Field Descriptions
Bit Field Type Reset Notes Description
7 ADC_EN R/W 0h Reset by:
WATCHDOG
REG_RST
 ADC Control
Type : RW
POR: 0b

0h = Disable

1h = Enable
6 ADC_RATE R/W 0h Reset by:
REG_RST
 ADC conversion rate control
Type : RW
POR: 0b

0h = Continuous conversion

1h = One shot conversion
5-4 ADC_SAMPLE_1:0 R/W 3h Reset by:
REG_RST
 ADC sample speed
Type : RW
POR: 11b

0h = 15 bit effective resolution

1h = 14 bit effective resolution

2h = 13 bit effective resolution

3h = 12 bit effective resolution (not recommended)
3 ADC_AVG R/W 0h Reset by:
REG_RST
 ADC average control
Type : RW
POR: 0b

0h = Single value

1h = Running average (not available for IBAT discharge)
2 ADC_AVG_INIT R/W 0h Reset by:
REG_RST
 ADC average initial value control
Type : RW
POR: 0b

0h = Start average using the existing register value

1h = Start average using a new ADC conversion
1-0 RESERVED R/W 0h RESERVED

9.5.1.43 REG2F_ADC_Function_Disable_0 Register (Offset = 2Fh) [reset = 0h]

REG2F_ADC_Function_Disable_0 is shown in Figure 9-68 and described in Table 9-56.

Return to the Summary Table.

ADC Function Disable 0

Figure 9-68 REG2F_ADC_Function_Disable_0 Register
7 6 5 4 3 2 1 0
IBUS_ADC_DIS IBAT_ADC_DIS VBUS_ADC_DIS VBAT_ADC_DIS VSYS_ADC_DIS TS_ADC_DIS TDIE_ADC_DIS RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h
Table 9-56 REG2F_ADC_Function_Disable_0 Register Field Descriptions
Bit Field Type Reset Notes Description
7 IBUS_ADC_DIS R/W 0h Reset by:
REG_RST
 IBUS ADC control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
6 IBAT_ADC_DIS R/W 0h Reset by:
REG_RST
 IBAT ADC control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
5 VBUS_ADC_DIS R/W 0h Reset by:
REG_RST
 VBUS ADC control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
4 VBAT_ADC_DIS R/W 0h Reset by:
REG_RST
 VBAT ADC control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
3 VSYS_ADC_DIS R/W 0h Reset by:
REG_RST
 VSYS ADC control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
2 TS_ADC_DIS R/W 0h Reset by:
REG_RST
 TS ADC control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
1 TDIE_ADC_DIS R/W 0h Reset by:
REG_RST
 TDIE ADC control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
0 RESERVED R 0h RESERVED

9.5.1.44 REG30_ADC_Function_Disable_1 Register (Offset = 30h) [reset = 0h]

REG30_ADC_Function_Disable_1 is shown in Figure 9-69 and described in Table 9-57.

Return to the Summary Table.

ADC Function Disable 1

Figure 9-69 REG30_ADC_Function_Disable_1 Register
7 6 5 4 3 2 1 0
DP_ADC_DIS DM_ADC_DIS VAC2_ADC_DIS VAC1_ADC_DIS RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R-0h
Table 9-57 REG30_ADC_Function_Disable_1 Register Field Descriptions
Bit Field Type Reset Notes Description
7 DP_ADC_DIS R/W 0h Reset by:
REG_RST
 D+ ADC Control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
6 DM_ADC_DIS R/W 0h Reset by:
REG_RST
 D- ADC Control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
5 VAC2_ADC_DIS R/W 0h Reset by:
REG_RST
 VAC2 ADC Control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
4 VAC1_ADC_DIS R/W 0h Reset by:
REG_RST
 VAC1 ADC Control
Type : RW
POR: 0b

0h = Enable (Default)

1h = Disable
3-0 RESERVED R 0h RESERVED

9.5.1.45 REG31_IBUS_ADC Register (Offset = 31h) [reset = 0h]

REG31_IBUS_ADC is shown in Figure 9-70 and described in Table 9-58.

Return to the Summary Table.

IBUS ADC

Figure 9-70 REG31_IBUS_ADC Register
15 14 13 12 11 10 9 8
IBUS_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
IBUS_ADC_15:0
R-0h
Table 9-58 REG31_IBUS_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 IBUS_ADC_15:0 R 0h

IBUS ADC reading
Reported in 2 's Complement.
When the current is flowing from VBUS to PMID, IBUS ADC reports positive value, and when the current is flowing from PMID to VBUS, IBUS ADC reports negative value.
Type : R
POR: 0mA (0h)
Range : 0mA-5000mA
Fixed Offset : 0mA
Bit Step Size : 1mA

9.5.1.46 REG33_IBAT_ADC Register (Offset = 33h) [reset = 0h]

REG33_IBAT_ADC is shown in Figure 9-71 and described in Table 9-59.

Return to the Summary Table.

IBAT ADC

Figure 9-71 REG33_IBAT_ADC Register
15 14 13 12 11 10 9 8
IBAT_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
IBAT_ADC_15:0
R-0h
Table 9-59 REG33_IBAT_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 IBAT_ADC_15:0 R 0h

IBAT ADC reading
Reported in 2 's Complement.
.
Type : R
POR: 0mA (0h)
Range : 0mA-8000mA
Fixed Offset : 0mA
Bit Step Size : 1mA
The IBAT ADC reports the battery charging current in forward mode and the battery discharging current in OTG and battery only (HiZ) mode if EN_BAT bit in REG14[5]=1. The sign bit is 0b for charging current and 1b for discharging current.

9.5.1.47 REG35_VBUS_ADC Register (Offset = 35h) [reset = 0h]

REG35_VBUS_ADC is shown in Figure 9-72 and described in Table 9-60.

Return to the Summary Table.

VBUS ADC

Figure 9-72 REG35_VBUS_ADC Register
15 14 13 12 11 10 9 8
VBUS_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
VBUS_ADC_15:0
R-0h
Table 9-60 REG35_VBUS_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 VBUS_ADC_15:0 R 0h

VBUS ADC reading.
Type : R
POR: 0mV (0h)
Range : 0mV-30000mV
Fixed Offset : 0mV
Bit Step Size : 1mV

9.5.1.48 REG37_VAC1_ADC Register (Offset = 37h) [reset = 0h]

REG37_VAC1_ADC is shown in Figure 9-73 and described in Table 9-61.

Return to the Summary Table.

VAC1 ADC

Figure 9-73 REG37_VAC1_ADC Register
15 14 13 12 11 10 9 8
VAC1_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
VAC1_ADC_15:0
R-0h
Table 9-61 REG37_VAC1_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 VAC1_ADC_15:0 R 0h

VAC1 ADC reading
Type : R
POR: 0mV (0h)
Range : 0mV-30000mV
Fixed Offset : 0mV
Bit Step Size : 1mV

9.5.1.49 REG39_VAC2_ADC Register (Offset = 39h) [reset = 0h]

REG39_VAC2_ADC is shown in Figure 9-74 and described in Table 9-62.

Return to the Summary Table.

VAC2 ADC

Figure 9-74 REG39_VAC2_ADC Register
15 14 13 12 11 10 9 8
VAC2_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
VAC2_ADC_15:0
R-0h
Table 9-62 REG39_VAC2_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 VAC2_ADC_15:0 R 0h

VAC2 ADC reading
Type : R
POR: 0mV (0h)
Range : 0mV-30000mV
Fixed Offset : 0mV
Bit Step Size : 1mV

9.5.1.50 REG3B_VBAT_ADC Register (Offset = 3Bh) [reset = 0h]

REG3B_VBAT_ADC is shown in Figure 9-75 and described in Table 9-63.

Return to the Summary Table.

VBAT ADC

Figure 9-75 REG3B_VBAT_ADC Register
15 14 13 12 11 10 9 8
VBAT_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
VBAT_ADC_15:0
R-0h
Table 9-63 REG3B_VBAT_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 VBAT_ADC_15:0 R 0h

The battery remote sensing voltage (VBATP) ADC reading
Type : R
POR: 0mV (0h)
Range : 0mV-20000mV
Fixed Offset : 0mV
Bit Step Size : 1mV

9.5.1.51 REG3D_VSYS_ADC Register (Offset = 3Dh) [reset = 0h]

REG3D_VSYS_ADC is shown in Figure 9-76 and described in Table 9-64.

Return to the Summary Table.

VSYS ADC

Figure 9-76 REG3D_VSYS_ADC Register
15 14 13 12 11 10 9 8
VSYS_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
VSYS_ADC_15:0
R-0h
Table 9-64 REG3D_VSYS_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 VSYS_ADC_15:0 R 0h

VSYS ADC reading
Type : R
POR: 0mV (0h)
Range : 0mV-24000mV
Fixed Offset : 0mV
Bit Step Size : 1mV

9.5.1.52 REG3F_TS_ADC Register (Offset = 3Fh) [reset = 0h]

REG3F_TS_ADC is shown in Figure 9-77 and described in Table 9-65.

Return to the Summary Table.

TS ADC

Figure 9-77 REG3F_TS_ADC Register
15 14 13 12 11 10 9 8
TS_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
TS_ADC_15:0
R-0h
Table 9-65 REG3F_TS_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 TS_ADC_15:0 R 0h

TS ADC reading
Type : R
POR: 0% (0h)
Range : 0%-99.9023%
Fixed Offset : 0%
Bit Step Size : 0.0976563%

9.5.1.53 REG41_TDIE_ADC Register (Offset = 41h) [reset = 0h]

REG41_TDIE_ADC is shown in Figure 9-78 and described in Table 9-66.

Return to the Summary Table.

TDIE_ADC

Figure 9-78 REG41_TDIE_ADC Register
15 14 13 12 11 10 9 8
TDIE_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
TDIE_ADC_15:0
R-0h
Table 9-66 REG41_TDIE_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 TDIE_ADC_15:0 R 0h

TDIE ADC reading
Reported in 2 's Complement.
Type : R
POR: 0°C (0h)
Range : -40°C-150°C
Fixed Offset : 0°C
Bit Step Size : 0.5°C

9.5.1.54 REG43_D+_ADC Register (Offset = 43h) [reset = 0h]

REG43_D+_ADC is shown in Figure 9-79 and described in Table 9-67.

Return to the Summary Table.

D+ ADC

Figure 9-79 REG43_D+_ADC Register
15 14 13 12 11 10 9 8
D+_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
D+_ADC_15:0
R-0h
Table 9-67 REG43_D+_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 D+_ADC_15:0 R 0h

D+ ADC reading
Type : R
POR: 0mV (0h)
Range : 0mV-3600mV
Fixed Offset : 0mV
Bit Step Size : 1mV

9.5.1.55 REG45_D-_ADC Register (Offset = 45h) [reset = 0h]

REG45_D-_ADC is shown in Figure 9-80 and described in Table 9-68.

Return to the Summary Table.

D- ADC

Figure 9-80 REG45_D-_ADC Register
15 14 13 12 11 10 9 8
D-_ADC_15:0
R-0h
7 6 5 4 3 2 1 0
D-_ADC_15:0
R-0h
Table 9-68 REG45_D-_ADC Register Field Descriptions
Bit Field Type Reset Description
15-0 D-_ADC_15:0 R 0h

D- ADC reading
Type : R
POR: 0mV (0h)
Range : 0mV-3600mV
Fixed Offset : 0mV
Bit Step Size : 1mV

9.5.1.56 REG47_DPDM_Driver Register (Offset = 47h) [reset = 0h]

REG47_DPDM_Driver is shown in Figure 9-81 and described in Table 9-69.

Return to the Summary Table.

DPDM Driver

Figure 9-81 REG47_DPDM_Driver Register
7 6 5 4 3 2 1 0
DPLUS_DAC_2:0 DMINUS_DAC_2:0 RESERVED
R/W-0h R/W-0h R/W-0h
Table 9-69 REG47_DPDM_Driver Register Field Descriptions
Bit Field Type Reset Description
7-5 DPLUS_DAC_2:0 R/W 0h

D+ Output Driver
Type : RW
POR: 000b

0h = HIZ

1h = 0

2h = 0.6V

3h = 1.2V

4h = 2.0V

5h = 2.7V

6h = 3.3V

7h = D+/D- Short
4-2 DMINUS_DAC_2:0 R/W 0h

D- Output Driver
Type : RW
POR: 000b

0h = HIZ

1h = 0

2h = 0.6V

3h = 1.2V

4h = 2.0V

5h = 2.7V

6h = 3.3V

7h = reserved
1-0 RESERVED R/W 0h

RESERVED

9.5.1.57 REG48_Part_Information Register (Offset = 48h) [reset = 0h]

REG48_Part_Information is shown in Figure 9-82 and described in Table 9-70.

Return to the Summary Table.

Part Information

Figure 9-82 REG48_Part_Information Register
7 6 5 4 3 2 1 0
RESERVED PN_2:0 DEV_REV_2:0
R-0h R-0h R-0h
Table 9-70 REG48_Part_Information Register Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R 0h

RESERVED
5-3 PN_2:0 R 3h

Device Part Number
011b = BQ25798
2-0 DEV_REV_2:0 R 1h

Device Revision
001b = BQ25798