SLUSDX3C november   2020  – august 2023 UCC25800-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Oscillator
      3. 8.3.3 External Synchronization
      4. 8.3.4 Dead-Time
        1. 8.3.4.1 Adaptive Dead-time
        2. 8.3.4.2 Maximum Programmable Dead-time
      5. 8.3.5 Protections
        1. 8.3.5.1 Overcurrent Protection
          1. 8.3.5.1.1 OCP Threshold Setting
          2. 8.3.5.1.2 Output Power Capability
        2. 8.3.5.2 Input Overvoltage Protection (OVP)
        3. 8.3.5.3 Over-Temperature Protection (TSD)
        4. 8.3.5.4 Pin-Fault Protections
        5. 8.3.5.5 VREG Pin Protection
      6. 8.3.6 DIS/FLT Pin operation
        1. 8.3.6.1 FAULT Codes
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Soft-start Mode
      3. 8.4.3 Normal Operation Mode
      4. 8.4.4 Disabled Mode
      5. 8.4.5 Fault Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 LLC Converter Operation Principle
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

8.3.3 External Synchronization

An external signal connected to the SYNC pin synchronizes the switching frequency of the UCC25800-Q1 transformer driver.

In the external synchronization mode, the switching frequency of the SW pin is half of the SYNC pin signal frequency. Given that, to ensure the output voltage remains within the normal operation range, the half of the frequency of external synchronization signal needs to be between 15% and 30% (nominal) above the programmed switching frequency with a tolerance of 5% or less, as described in Equation 2. A minimum high and low pulse width of 150 ns is required. The SYNC pin logic is compatible with TTL and CMOS levels for the design simplicity. It is recommended to use 50% duty cycle signal.

Equation 2. 1.15 × f S W < 1 2 × f S Y N C < 1.3 × f S W

where

  • fSW is the RT pin programmed SW-pin switching frequency
  • fSYNC is the SYNC pin signal frequency

The transformer driver ignores the external synchronization signal during the 1.5-ms soft-start time. The switching frequency during the soft-start time is based on the RT pin voltage as described in Section 8.3.2. After the soft-start period ends, if an external synchronization signal is present and its frequency and pulse width are within the specified range, the switch node is driven by the SYNC pin signal. The transformer driver also integrates a hand-off algorithm so that when the switching frequency transitions from internal oscillator to the external synchronization signal, the disturbance is minimal and transformer saturation is avoided.

The hand-off algorithm first confirms that the external synchronization signal is within the range. If the frequency is not within the acceptable range, the hand-off doesn't happen. If the frequency is within the acceptable range, the hand-off algorithm begins to search for the optimal transition point and locks the switching frequency with the external SYNC signal. After the frequency is locked, the hand-off algorithm stops monitoring the SYNC pin frequency. It is important to ensure external synchronization source has a stable frequency. There is an internal watchdog timer to prevent the external frequency from falling below the set frequency (the watchdog time does not monitor if the SYNC pin frequency goes above the range). If the SYNC pin frequency drops below the set frequency, the transformer driver loses synchronization and the converter operates with the set frequency determined by RT pin voltage.

The Figure 8-5 shows an oscilloscope screen capture for the controller transition from internal oscillator to the external synchronization signal. The smooth transition can be observed and the SW pin current sees minimal disturbance.

GUID-491A0DE6-766D-4F0B-8EAF-28FBE1A3D53D-low.gif Figure 8-5 Transition from internal oscillator to external synchronization

The internal MOSFET gate drives are toggled on each SYNC pin voltage rising edge, so the switch-node frequency is equal to half of the SYNC pin signal frequency, as shown in Figure 8-6. Due to the internal filter delays, the SW pin switching edge is not aligned with the SYNC pin switching edge. There is a delay of approximately 150 ns.

GUID-20211104-SS0I-LPGS-GQFF-HRNPZPCXWZ3R-low.svg Figure 8-6 External SYNC signal drives switching frequency