SLUSE44D April   2020  – May 2024 UCC27624

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Supply Current
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
      5. 6.3.5 Low Propagation Delays and Tightly Matched Outputs
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD and Undervoltage Lockout
        2. 7.2.2.2 Drive Current and Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Unless otherwise noted, VDD = 12 V, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, no load on the output. Typical condition specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS CURRENTS
IVDDq VDD quiescent supply current VINx = 3.3 V, VDD = 3.4 V, ENx = VDD 300 450 μA
IVDD VDD static supply current VINx = 3.3 V, ENx = VDD 0.6 1.0 mA
IVDD VDD static supply current VINx = 0 V, ENx = VDD 0.7 1.0 mA
IVDDO VDD operating current fSW = 1000 kHz, ENx = VDD, VINx = 0 V – 3.3 V PWM 3.2 3.8 mA
IDIS VDD disable current VINx = 3.3 V, ENx = 0 V 0.8 1.1 mA
UNDERVOLTAGE LOCKOUT (UVLO)
VVDD_ON VDD UVLO rising threshold 3.8 4.1 4.4 V
VVDD_OFF VDD UVLO falling threshold 3.5 3.8 4.1 V
VVDD_HYS VDD UVLO hysteresis 0.3 V
INPUT (INA, INB)
VINx_H Input signal high threshold Output High, ENx = HIGH 1.8 2 2.3 V
VINx_L Input signal low threshold Output Low, ENx = HIGH 0.8 1 1.2 V
VINx_HYS Input signal hysteresis 1 V
RINx INx pin pulldown resistor INx = 3.3 V 120 kΩ
ENABLE (ENA, ENB)
VENx_H Enable signal high threshold Output High, INx = HIGH 1.8 2 2.3 V
VENx_L Enable signal low threshold Output Low, INx = HIGH 0.8 1 1.2 V
VENx_HYS Enable signal hysteresis 1 V
RENx EN pin pullup resistance ENx = 0 V 200 kΩ
OUTPUTS (OUTA, OUTB)
ISRC(1) Peak output source current VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz 5 A
ISNK(1) Peak output sink current VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz –5 A
ROH(2) Pullup resistance IOUT = –50 mA, See Section 6.3.4. 5 8.5 Ω
ROL Pulldown resistance IOUT = 50 mA 0.6 1.1 Ω
(1) Parameter not tested in production.
(2) Output pullup resistance in this table is a DC measurement that measures resistance of PMOS structure only (not N-channel structure).