DATA SHEET
UCC14240-Q1 Automotive 2.0-W, 24-V VIN, 25-V VOUT, High-Density, > 3 kVRMS, Isolated DC/DC Module
1 Features
- Fully integrated high-density isolated DC/DC module with isolation transformer
- Isolated DC/DC for driving: IGBTs, SiC FETs
- Input voltage range: 21 V to 27 V with 32-V absolute maximum
- 2.0-W output power at TA ≤ 85°C and > 1.5 W at TA = 105 °C
- Adjustable (VDD – VEE) output voltage (with external resistors): 18 V to 25 V, ±1.3 % regulation accuracy over full temperature range
- Adjustable (COM – VEE) output voltage (with external resistors): from 2.5 V to (VDD – VEE), ±1.3 % regulation accuracy over full temperature range
- Low electromagnetic emission with spread spectrum modulation and integrated transformer design
- Enable, Power Good, UVLO, OVLO, soft-start, short-circuit, power-limit, under-voltage, over-voltage, and over-temperature protection
- CMTI > 150 kV/µs
- AEC-Q100 qualified for automotive applications
- Temperature grade 1: –40°C ≤ TJ ≤ 150°C
- Temperature grade 1: –40 °C ≤ TA ≤ 125°C
- Functional Safety-Capable
- Planned safety-related certifications:
- 4243-VPK basic isolation per DIN EN IEC 60747-17 (VDE 0884-17)
- 3000-VRMS isolation for 1 minute per UL1577
Basic insulation per CQC GB4943.1
- 36-pin, wide SSOP package
3 Description
UCC14240-Q1 is an automotive qualified high isolation voltage DC/DC power module designed to provide power to IGBT or SiC gate drivers. The UCC14240-Q1 integrates a transformer and DC/DC controller with a proprietary architecture to achieve high efficiency with very low emissions. The high-accuracy output voltages provide better channel enhancement for higher system efficiency without over-stressing the power device gate.
The UCC14240-Q1 provides up to 2.0 W (typical) of isolated output power at high efficiency. Requiring a minimum of external components and including on-chip device protection, the module provides extra features such as input undervoltage lockout, overvoltage lockout, output voltage power-good comparators, overtemperature shutdown, soft-start time-out, adjustable isolated positive and negative output voltage, an enable pin, and an open-drain output power-good pin.
Package Information
| ORDERABLE PART NUMBER(1) | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| UCC14240QDWNRQ1 | DWN (SSOP, 36) | 12.83 mm × 7.50 mm |
(1) For all available packages, see the orderable addendum at the end of the data sheet.
Simplified Application
Typical Power-up Sequence5 Pin Configuration and Functions
Figure 5-1 DWN Package, 36-Pin SSOP (Top View)
Table 5-1 Pin Functions
| PIN | TYPE (1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| GNDP | 1, 2, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 | G | Primary-side ground connection for VIN. PIN 1,2, and 5 are analog ground. PIN 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are power ground. Place several vias to copper pours for thermal relief. See Layout Guidelines. |
| PG | 3 | O | Active low power-good open-drain output pin. PG remains low when (UVLO ≤ VVIN ≤ OVLO); (UVP1 ≤ (VDD – VEE) ≤ OVP1); (UVP2 ≤ (COM – VEE) ≤ OVP2); TJ_Primary ≤ TSHUTPPRIMARY_RISE; and TJ_secondary ≤ TSHUTSECONDARY_RISE |
| ENA | 4 | I | Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5-V recommended maximum. |
| VIN | 6, 7 | P | Primary input voltage. PIN 6 is for analog input, and PIN 7 is for power input. For PIN 7, connect one 10-µF ceramic capacitor from power VIN PIN 7 to power GNDP PIN 8. Connect a 0.1-µF high-frequency bypass ceramic capacitor close to PIN 7 and PIN 8. Optionally, connect a 330pF 0402 size high-frequency bypass ceramic capacitor close to analog VIN PIN 6 and GNDP PIN 5. |
| VEE | 19, 20, 21, 22, 23, 24, 25,26, 27, 30,31, 36 | G | Secondary-side reference connection for VDD and COM. The VEE pins are used for the high current return paths. |
| VDD | 28, 29 | P | Secondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 0.1-µF ceramic capacitor from VDD to VEE. The 0.1-µF ceramic capacitor is the high frequency bypass and must be next to the IC pins. A 4.7-µF or 10-µF ceramic capacitor can be used instead of 2.2 to further reduce the output ripple voltage. |
| RLIM | 32 | P | Secondary-side second isolated output voltage resistor to limit the source current from VDD to COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to regulate the (COM – VEE) voltage. See RLIM Resistor Selection for more detail. |
| FBVEE | 33 | I | Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and the equivalent FBVEE voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVEE and VEEA IC pins on top layer or back layer connected with vias. |
| FBVDD | 34 | I | Feedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage. Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVDD and VEEA IC pins on top layer or back layer connected with vias. |
| VEEA | 35 | G | Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs, FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the VEEA pin. See Layout Guidelines. |
(1) P = power, G = ground, I = input, O = output
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
| Parameter | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|
| VIN to GNDP | –0.3 | 32 | V | ||
| ENA, PG to GNDP | –0.3 | 7 | V | ||
| VDD, RLIM, FBVDD, FBVEE to VEE | –0.3 | 32 | V | ||
| PLOSS_MAX | Total power loss at TA=25°C | 2.45 | W | ||
| POUT_VDD_MAX | Total (VDD – VEE) output power at TA=25°C | 2.5 | W | ||
| IRLIM_MAX_RMS_SOURCE | Max RLIM pin rms current sourcing from VDD to RLIM. (16% average run time over lifetime of 24,500 hr) | 0.125 | ARMS | ||
| IRLIM_MAX_RMS_SINK | Max RLIM pin rms current sinking from RLIM to VEE. (16% average run time over lifetime of 24,500 hr) | 0.125 | ARMS | ||
| TJ | Operating junction temperature range | –40 | 150 | °C | |
| Tstg | Storage temperature | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
