SLUSE80C September   2021  – December 2022 UCC14240-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Electrical Characteristics
    9. 6.9  Safety Limiting Values
    10. 6.10 Insulation Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-VEE Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 Power Handling Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and PG
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Overvoltage Protection
        4. 7.3.4.4 Overpower Protection
          1. 7.3.4.4.1 Output Undervoltage Protection
        5. 7.3.4.5 Overtemperature Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 RLIM Resistor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

8.5.1 Layout Guidelines

The UCC14240-Q1 integrated isolated power solution simplifies system design and reduces board area usage. Follow these guidelines for proper PCB layout to achieve optimum performance.

  • Place decoupling capacitors as close as possible to the device pins. For the input supply, place the capacitors between pin 7 (power VIN) and pins 8–18 (power GNDP), and place the capacitors between pin 6 (analog VIN) and pins 1, 2, and 5 (analog GNDP). For the isolated output supply, place the capacitors between pin 28, 29 (VDD) and pins 19–25, 30–31, 35–36 (VEE). This location is of particular importance to the input decoupling capacitor because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits.

    The capacitors between pin 6 (analog VIN) and pins 1, 2, and 5 (analog GNDP) are optional and recommended.

  • Because the device does not have a thermal pad for heat-sinking, the device dissipates heat through the respective GND pins. Ensure that enough copper (preferably a connection to the ground plane) is present on GNDP and VEE pins for best heat-sinking.
  • If space and layer count allow, TI recommends to connect the VIN, GNDP, VDD, and VEE pins to internal ground or power planes through multiple vias. Alternatively, make the traces that are connected to these pins as wide as possible to minimize losses.
  • Minimize capacitive coupling between the RLIM pin and the FBVEE pin by separating the traces while routing, and if possible use a via near the FBVEE pin to route the feedback connection through a different layer.
  • A minimum of four layers is recommended to accomplish a good thermal PCB design. Inner layers can be used to create a high-frequency bypass capacitor between GNDP and VEE, which in turn mitigates radiated emissions.
  • Pay close attention to the spacing between primary ground plane (GNDP) and secondary ground plane (VEE) on the outer layers of the PCB. The effective creepage and clearance of the system is reduced if the two ground planes have a lower spacing than that of the UCC1413x-Q1 package.
  • To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or copper below the UCC14240-Q1 module.