SLUSE80C September   2021  – December 2022 UCC14240-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Electrical Characteristics
    9. 6.9  Safety Limiting Values
    10. 6.10 Insulation Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-VEE Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 Power Handling Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and PG
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Overvoltage Protection
        4. 7.3.4.4 Overpower Protection
          1. 7.3.4.4.1 Output Undervoltage Protection
        5. 7.3.4.5 Overtemperature Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 RLIM Resistor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

8.2.2.2 RLIM Resistor Selection

When the module is configured as dual-positive or dual-negative outputs, the RLIM resistor is a true current limiting resistor. Set up the RLIM resistor value as the maximum load current needed for VCOM-VEE, using Equation 6. IVOUT2_max is the maximum load current for VCOM-VEE output.

Equation 6. RLIM=VCOM-VEEI(VDD-COM)_max -RLIM_INT

RLIM_INT is the internal switch resistance value of 30 Ω typical.

For isolated gate driver applications, one positive and one negative outputs are needed. In this case, VDD-VEE is the total output voltage, and the middle point becomes the reference point. Because the total voltage between VDD and VEE is always regulated through the FBVDD feedback, the RLIM pin only must regulate the middle point voltage so that it can give the correct positive and negative voltages. The RLIM control is achieved through FBVEE pin as described in Section 7.3.1.2.

Based on Section 8.2.2.1, when selecting the output capacitor ratio proportional to the voltage ratio, the capacitors form a voltage divider. The middle point voltage must naturally give the correct positive and negative voltages. At the same time, for the gate driver circuit, the gate charge pulled out from the positive rail capacitor during turn-on is fed back to the negative rail capacitor during turn-off, the two output rail load must always be balanced. However, due to the gate driver circuit quiescent current unbalancing, and the two-rail capacitance tolerances, the middle point voltage can move away with time. The RLIM pin provides an opposite current to keep the middle point voltage at the correct level.

As illustrated in Figure 8-3 (a), without considering the gate charge, the gate driver circuit quiescent current loads the positive rail and negative rail differently. The net current shows up as a DC offset current to the middle point.

As illustrated in Figure 8-3 (b), every time the gate driver circuit turns-on the main power switch, it pulls the charge out of the positive and negative rail output capacitors. When the module power stage provides energy to the secondary side, refreshing those capacitors, the same charge is fed into both capacitors. If the capacitor values are perfect, the voltage rise in the capacitors will be proportional. The positive and negative voltages would not change. However, due to the capacitor tolerances, the capacitor values are not perfectly matched. The voltages will rise at different ratios with the smaller capacitor rising faster. Over time, the middle point voltage, COM, would pull to a different value. A load across one of the capacitors will pull towards a voltage imbalance. The RLIM function counteract the voltage imbalance and bring the COM voltage back into regulation.

(a) Load current unbalancing(b) Capacitance unbalancing

Figure 8-3 Source of voltage unbalancing

Considering these two effects, the RLIM must provide enough current to compensate this offset current. The RLIM must be low enough to provide enough current, but not too low otherwise the middle point voltage is corrected at each turn on and turn off edge of the gate driver and excessive power loss is generated.

The RLIM resistor chosen can provide enough current for the load using the following equations, whichever has lower RLIM value. Equation 7 shows source current due to capacitor variation and gate driver quiescent current (IQ). Equation 8 shows sink current due to capacitor variation and IQ.

Equation 7. RLIM_MAX=VDD-COMCOUT3×1 - ∆COUT3COUT2×1 - ∆COUT2 + COUT3×1 - ∆COUT3 - COUT3COUT2 + COUT3×QG_Total×fSW + I(COM-VEE) - I(VDD-COM) -RLIM_INT
Equation 8. RLIM_MAX=VEE-COMCOUT2×1 - ∆COUT2COUT2×1 - ∆COUT2 + COUT3×1 - ∆COUT3 - COUT2COUT2 + COUT3×QG_Total×fSW + I(COM-VEE) - I(VDD-COM) - RLIM_INT

Select RLIM value to be the lowest of either 1) the RLIM needed for capacitor imbalance and the load, or 2) the RLIM needed to respond to a 10% overshoot of VCOM-VEE within 1.5 ms with the given load current.

Equation 9. RLIM_MAX_for_overshoot=VCOM-VEECOUT3_max×0.10×VVDD-COM1.5 ms+I(VDD-COM)-I(COM-VEE) -RLIM_INT
where

  • QG_Total is the total gate charge of power switch.
  • fSW is the switching frequency of gate drive load.

RLIM value determines response time of (COM – VEE) regulation. Too low an RLIM value can cause oscillation and can overload (VDD – VEE). Too high an RLIM value can give offset errors, due to slow response. If RLIM is greater than above calculations, then there is not enough current available to replenish the charge to the output capacitors, causing a charge imbalance where the voltage is not able to maintain regulation, and eventually exceeds the OVP2 or UVP2 FAULT thresholds and shutting down the device for protection. Choose RLIM value to be 10% less than the smaller value of the two calculated results.