The VS pin senses the negative voltage level of the auxiliary winding during the on-time of the primary-side switch (Q_L) to detect an under-voltage condition of the input DC or AC line. When the bulk voltage (V_BULK) is too low, UCC28781-Q1 stops switching and no V_O restart attempt is made until the input line voltage is back into normal range. As Q_L turns on with PWML, the negative voltage level of the auxiliary winding voltage (V_AUX) is equal to V_BULK divided by primary-to-auxiliary turns ratio (N_PA) of the transformer, which is N_P / N_A. During this time, the voltage on VS pin is clamped to about 250 mV below AGND. As a result, V_AUX can create a line-sensing current (I_VSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (R_VS1). With I_VSL proportional to V_BULK, it can be used to compare against two under-voltage thresholds, I_VSL(RUN) and I_VSL(STOP).

The following discussion, equations, and figures involving brown-in and brown-out thresholds are based on AC-line input conditions, but are generally applicable to DC input voltages as well. For an application using a DC input, substitute V_DC(BI) for V_AC(BI), V_DC(BO) for V_AC(BO) and remove the √2 factor from each equation and figure in this section.

The target brown-in AC voltage (V_AC(BI)) can be programmed by the proper selection of R_VS1. For every UVLO cycle of VDD, there are at least four initial test pulses from PWML to check I_VSLcondition. I_VSL of the first test pulse is ignored. If I_VSL ≤ I_VSL(RUN) is valid for the next three consecutive test pulses, the controller stops switching, the RUN pin goes low, and a new UVLO start cycle is initiated after V_VDD reaches V_VDD(OFF). On the other hand, if I_VSL > I_VSL(RUN) occurs, V_O soft start sequence is initiated.

The brown-out AC voltage (V_AC(BO)) is set internally by approximately 83% of V_AC(BI), which provides enough hysteresis to compensate for possible sensing errors through the auxiliary winding.

A 60-ms timer (t_BO) is used to bypass the effect of line ripple content on the I_VSL sensing. Only when the I_VSL ≤ I_VSL(STOP) condition lasts longer than 60 ms (i.e. typically three line cycles of 50 Hz) and 3 additional switching cycles verify the condition, the brown-out fault is triggered. If switching is interrupted, the brown-out fault will remain pending without shut-down until the 3 verification cycles complete. The fault is reset after V_VDD reaches V_VDD(OFF). Figure 7-37 shows an example of the timing sequence of brown-out and brown-in protections for the case of an actual input brown-out condition. An application with DC input that has considerable ripple on the bulk voltage will behave similar to the AC-line bulk-ripple case.

The t_BO timer is started at the moment I_VSL ≤ I_VSL(STOP) is detected during the PWML on-time. The timer is cleared when I_VSL > I_VSL(STOP) is detected. In the case of an overshoot voltage on the output, switching will stop until the output voltage recovers to the regulation level. If the t_BO timer is triggered by I_VSL ≤ I_VSL(STOP) while in the valley of the bulk ripple voltage, and then switching is stopped the status of I_VSL cannot be detected and updated. The timer cannot be cleared without switching to sample I_VSL, and the 60-ms timer may elapse even though no brown-out condition exists. To prevent an unwarranted shut-down, the 3 additional switching cycles sample the condition once switching does resume, to verify or dismiss the pending apparent brown-out fault. An extended output overshoot condition longer than t_BO can result from a sudden load drop combined with a drop in the regulation reference due to reduction of cable compensation. Figure 7-38 shows an example of the timing sequence for the case of an apparent brown-out cancelled by 3 verifying pulses.