SLUSEI6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

EMI Dither and Dither Fading Function

The frequency dither function in AAM reduces the conducted EMI noise and results in EMI filter size reduction. Conventionally, the dither carrier frequency is in the range of hundreds of Hz. However, when the control loop bandwidth is pushed higher in order to improve the load transient response, the control loop will be able to correct the disturbance from the dither signal, and weakens the EMI frequency spreading effectiveness. Even though increasing the dither frequency to few kHz can reduce the influence of the control loop, the audible noise issue will occur. For UCC28781-Q1, since itis able to run at a higher switching frequency in AAM, the dither frequency can be optimized at 23 kHz, so as to avoid audible noise and desensitize the loop response effect on the EMI attenuation.

UCC28781-Q1 enhances the response of the ZVS control loop, such that the ZVS performance can be maintained in most switching cycles even under a strong EMI dither condition. A triangular dither signal is superimposed on the feedback voltage signal VCST, The novel feed-forward control method is applied to allow the ZVS loop to correct the timing error much faster, so ZVS can be maintained and the efficiency will not suffer.

Conventionally, the dither magnitude is fixed across the whole output voltage range. Since the higher output voltage condition needs to deliver a higher output power, the EMI issue is typically more severe, so a stronger dither signal is needed for more conducted EMI reduction. In the lower output voltage condition, the output ripple specification is usually much tighter, so a strong dither signal may aggravate the output voltage ripple and create the design tradeoff. For UCC28781-Q1, the two-level dither magnitude is adjusted automatically based on the output voltage level, so the perturbed output ripple at the lower output voltage condition can be reduced to meet a more stringent ripple requirement, and the strong dither can still be applied to the higher output voltage condition for the better EMI performance. Specifically, when VVS is lower than 2.4 V during the demagnetization time (the LOW_NVO logic signal is high), the peak-to-peak dither magnitude on CS pin is reduced to around 36 mV. When VVS is higher than 2.5 V, the peak-to-peak dither magnitude on CS pin is increased to around 98 mV.

Since the low-line efficiency usually determines the power stage thermal limit, the efficiency will drop further when EMI dither is enabled. Since the bulk capacitor ripple voltage at low line is bigger than at high line and AAM mode forces variable frequency operation, the line frequency causes nature dither frequency anyway even without applying the internal EMI dither. Therefore, taking advantage of AAM mode, the dither function at low line can be disabled based on the brown-in voltage setting, so the option provides design flexibility to trade-off the worst-case low-line efficiency and EMI. Specifically, when iVSL is higher than 646 μA, the EMI dither function is enabled. When iVSL is lower than 580 μA, the EMI dither function is disabled. If the brown-in point is set at 75 Vac, this means that the EMI dither is disabled for 90 Vac and 115 Vac.

The dither fading feature allows the dither signal to be smoothly disabled, when the output load current is close to the transition point between AAM and ABM. As shown in Figure 7-25, VCST(MAX) and VCST(BUR) are used as the two voltage-clamping targets to the perturbed VCST signal. When the VCST reaches VCST(MAX), the top of the VCST ripple content is clipped by the internal clamp circuit, so the influence of the EMI dither on the peak power capability can be eliminated. When the VCST reaches VCST(BUR), the bottom of the VCST ripple content is clipped by an another internal clamp circuit, so the influence of the EMI dither on the ABM waveform is removed.

GUID-FFA1DE1C-7415-461A-B592-BBF2695F09BD-low.gifFigure 7-25 Dither Fading Feature in AAM