The PWML pin is the primary-side switch gate-drive, for which ground return is referenced to the PGND pin. The strong driver with 0.5-A peak source and 1.9-A peak sink capability can control either a silicon power MOSFET with a higher gate-to-source capacitance, a cascode GaN, an E-mode gate-injection-transistor (GIT) GaN with continuous on-state current, or a GaN power IC with logic PWM input.

The maximum voltage level of PWML is clamped to the P13 pin voltage. The 13-V clamped gate voltage provides an optimal gate-drive for low on-state resistance and lower gate-driving loss. An external gate resistor in parallel with a fast recovery diode can be used to further reduce the turn-on speed without compromising the turn-off switching loss. Slower turn-on speed of the primary switch mitigates the voltage stress across the secondary-side rectifier when the SR switch is disabled in deep light-load condition, and reduces the switching-node dV/dt to a safe level for reducing stress on the high-voltage isolating SR driver. A decoupling capacitor much larger than the PWML capacitive loading should be placed between P13 and PGND pins to decouple the gate-drive loop to allow operation at higher switching frequency. The 15-ns propagation delay of the PWML driver enables a higher frequency operation and more consistent ZVS switching.

Figure 7-14 and Figure 7-15 shows the example PWML driving network for a GIT GaN device and for a silicon MOSFET. Resistor R_G2 controls the turn-on speed. The turn-off speed can be maintained by the two fast recovery diodes, D_G1 and D_G2. R_G1 provides a continuous driving path to maintain the on state and low on-resistance (R_DS(on)) of a GIT GaN. C_G avoids the small R_G2 from affecting the on state current. PGND can be directly connected to the separate source terminal of a GIT GaN to achieve a kelvin connection, so the driver loop parasitic inductance can be decoupled.

An internal low-voltage level shifter is included between PGND and the ground return pin for analog control signals (AGND), so PGND can be connected separately to the top of the current sense resistor (R_CS) to achieve a Kelvin connection. When hard switching condition occurs, the lumped parasitic capacitor on the switch node is discharged, so a positive voltage spike is created across R_CS. In soft switching condition, the negative magnetizing current flowing through R_CS can create a negative voltage spike on R_CS. The level shifter is designed to handle 5-V positive transient spike and -1-V negative stress between PGND pin and AGND pin.