Designing for high power density requires consideration of noise coupling and thermal management. A four-layer PCB structure is highly recommended to use inner layers to help reduce current-loop areas and provide heat-spreading for surface-mount semiconductors.
Provide internal-layer copper areas to improve heat dissipation of high-power SMDs, particularly for switching MOSFETs and power diodes. Use multiple thermal-vias to conduct heat from outer pads to inner-layers and supporting copper areas.
To avoid capacitive noise coupling, do not cross outer-layer signals over copper areas that carry high-frequency switching voltage.
To avoid inductive noise coupling, keep switching current loops as small as possible, and do not run signal tracks in parallel with such loops.
Arrange the conducted-EMI filter components such that they do not allow switching noise to bypass them and affect the input. Avoid running switching signals through the EMI filter area.
Use multiple vias to connect high-current tracks and planes between layers.
Figure 10-1 summarizes the critical layout guidelines, and more detail is further elaborated in the descriptions below.
Figure 10-1 Typical Schematic with Layout Considerations