SLUSEI6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V, VSWS = 0 V, IFB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 µF, CP13 = 1 µF, and -40⁰C < TJ = TA < 125⁰C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VDD INPUT
IRUN(STOP)Supply current, run stateNo switching0.882.22.66mA
IRUN(SW)Supply current, run stateSwitching, IVSL = 0 µA2.4533.55mA
IWAITSupply current, wait stateIFB = -85 µA, IVDD only465540658µA
ISTARTSupply current, start stateVVDD = VVDD(ON) - 100 mV, VVS = 0 V150235301µA
IFAULTSupply current, fault statefault state500630µA
IVDD(LIMIT)VDD startup current limit during startupVVDD increasing, VSWS - VVDD = 1 V, VVDD = 16.5 V1.222.53mA
VVDD(ON)VDD turnon thresholdVVDD increasing16.21717.91V
VVDD(OFF)VDD turnoff thresholdVVDD decreasing9.9410.611.17V
VVDD(PCT)Offset to power cycle for long output voltage overshootOffset above VVDD(OFF), IFB = -85 µA1.542.22.98V
P13 OUTPUT
VP13P13 voltage level including load regulation0 mA to 60 mA out of P13, run state, VVDD = 20 V12.012.813.6V
IP13(START)Max sink current of P13 pin during startupVP13 = 14 V1.532.23.04mA
IP13(MAX)Current sourcing limit of P13 pinP13 shorted to AGND, VVDD = 20 V103.3133160mA
VR13(LINE)Line regulation of VP13VVDD = 15 V to 35 V-628.7mV
VP13(OV)Over voltage fault threshold above VP131.3522.54V
RP13Dropout resistance of P13 regulator switch between VDD and P13 pins(VVDD - VP13) / 30 mA, VVDD = 11 V, 30 mA out of P138.51322.7Ω
S13 OUTPUT
RS13RDS(on) of internal disconnect switch between P13 and S13 pins(VP13 - VS13) / 30 mA, VVDD = 11 V, 30 mA out of S132.12.83.82Ω
VS13_OKS13_OK threshold to enable switchingVRUN = 5 V9.6310.210.7V
IS13(MAX)Current sourcing limit of S13 pinS13 shorted to AGND, VVDD = 20 V260.7350452.5mA
REF OUTPUT
VREFREF voltage levelIREF = 0 A4.955.13V
IREF(MAX)Current sourcing limit of REF pinREF shorted to AGND, VVDD = 20 V14.31720.3mA
VR5(LINE)Line regulation of VREFVVDD = 12 V to 35 V-7-31mV
VR5(LOAD)Load regulation of VREF0 mA to 1 mA out of REF, Change in VREF-160.125mV
VS INPUT
VVSNCNegative clamp levelIVSL = -1.25 mA, voltage below ground221287344mV
VZCDZero-crossing detection (ZCD) levelVVS decreasing12.43567.2mV
IVSBInput bias currentVVS = 4 V-0.2300.31µA
VVS(SM1)VS threshold voltage in SM1 startup mode242.4282318.3mV
VVS(SM2)VS threshold voltage in SM2 startup mode458.3500543mV
VVSLV(UP)VS upper threshold out of low output voltage mode (LV mode)VVS increasing2.412.492.6V
VVSLV(LR)VS lower threshold into low output voltage mode (LV mode)VVS decreasing2.32.392.49V
tZCZero-crossing timeout delay1.952.32.73µs
tD(ZCD)Propagation delay from ZCD high to PWML 10% highVVS step from 4 V to -0.1 V

23

50

81

ns
CS INPUT
VCST(MAX)Peak-power threshold on CS pin out of LV modeIVSL = 0 μA, VVS ≥ VVSLV(UP)767.4801836.4mV
IVSL = -333 μA, VVS ≥ VVSLV(UP)650727788.7mV
IVSL = -666 μA, VVS ≥ VVSLV(UP)570600651.8mV
IVSL = -1.25 mA, VVS ≥ VVSLV(UP)537.2570612mV
VCST(MAX)_LVPeak-power threshold on CS pin in LV modeIVSL = 0 mA, VVS ≤ VVSLV(LR)593.7628663.9mV
IVSL = -666 μA, VVS ≤ VVSLV(LR)540570609.5mV
IVSL = -1.25 mA, VVS ≤ VVSLV(LR)511.2540584.7mV
VCST(MIN)Minimum CS threshold voltageVCS increasing, IFB = -85 µA120.7153200.1mV
KLCLine-compensation current ratioIVSL = -1.25 mA, IVSL / current out of CS pin21.62529A/A
VCST(EMI)(1)EMI dithering magnitude on CS pin out of LV mode(VBUR / KBUR-CST) < VCST < VCST(MAX), IVSL > -646 μA, VVS ≥ VVSLV(UP)78.496113.6mV
VCST(EMI)_LV(1)EMI dithering magnitude on CS pin in LV mode(VBUR / KBUR-CST) < VCST < VCST(MAX), IVSL > -646 μA, VVS ≤ VVSLV(LR)29.33642.7mV
VCST(SM1)CS threshold voltage in SM1 startup modeVVS < VVS(SM1)177.5200222.9mV
VCST(SM2)CS threshold voltage in SM2 startup modeVVS < VVS(SM2)470.4500531.4mV
tCSLEBLeading-edge-blanking timeVSET = 5 V, VCS = 1 V171.2190216.1ns
VSET = 0 V, VCS = 1 V94.4108125ns
tD(CS)Propagation delay of CS comparator high to PWML 90 % lowVCS step from 0 V to 1 V102637ns
fDITHER(1)EMI dithering frequency on CS pin(VBUR / KBUR-CST) < VCST < VCST(OPP), IVSL > -646 μA202327kHz
BUR INPUT and Low-power MODE
KBUR-CSTRatio of VBUR to VCSTVBUR between 0.7 V and 2.4 V3.823.984.09V/V
IBUR(LPM)Bias source current of VBUR offset in LPM2.092.653.16µA
IBUR(AAM)Bias sink current of VBUR offset in AAMVCST > VBUR / KBUR-CST3.764.855.81µA
fBUR(UP1)First upper threshold of burst frequency in ABM30.734.438.5kHz
fBUR(UP2)Second upper threshold of burst frequency in ABMVVS = 2.2 V41.851.258.9kHz
fBUR(LR)Lower threshold of burst frequency in ABM21.324.528.1kHz
fLPMBurst frequency in low-power mode23.32526.9kHz
IPC INPUT and SBP2 MODE
VCST_IPC(UP)Highest programmable VCST range of SBP2 by IPC pinVIPC = 5 V373.8405438.5mV
KIPCRatio of the programmable IPC voltage to VCSTVIPC between 1.8 V and 3.8 V59.36468.4mV/V
VCST_IPC(LR)Lowest programmable VCST range of SBP2 by IPC pinVIPC = 1 V247.5273307.7mV
VCST_IPC(MIN)Minimum VCST of SBP2 by grounding IPC pinVIPC = 0 V128.1154191.5mV
IIPC(SBP2)Bias source current of VIPC offset in SBP2IFB = -85 µA40.74955.7µA
fSBP2(UP)Upper threshold of burst frequency in SBP268.513.4kHz
fSBP2(LR)Lower threshold of burst frequency in SBP2VIPC = 2 V11.72kHz
RUN
VRUNHRUN pin high-levelIRUN = -0.2 mA4.64.785V
VRUNLRUN pin low-levelIRUN = 1 mA

0.1

0.25

0.3

V

ISRC(RUN)RUN peak source currentVRUN = 2.3 V334452mA
VRUN = 3 V142025mA
tR(RUN)Turn-on rise time of RUN pin, from 0 V to 2.5 VCLOAD = 22 nF, VRUN from 0 V to 2.5 V0.20.791µs
tF(RUN)Turn-off fall time of RUN pin, 90 % to 10 %CLOAD = 10 pF2032ns
PWML
VPWMLHPWML pin high-levelIPWML = -1 mA12.112.8513.6V
VPWMLLPWML pin low-levelIPWML = 1 mA0.0020.1V
ISRC(PWML)(1)PWML peak source currentVPWML = 0 V0.250.50.8A
ISNK(PWML)(1)PWML peak sink currentVPWML = 13 V1.21.92.8A
RSRC(PWML)PWML pull-up resistanceIPWML = -20 mA3.14.36.1Ω
RSNK(PWML)PWML pull-down resistanceIPWML = 20 mA0.51.11.9Ω
tR(PWML)Turn-on rise time of PWML pin, 10 % to 90 %CLOAD = 1.5 nF3053ns
tF(PWML)Turn-off fall time of PWML pin, 90 % to 10 %CLOAD = 1.5 nF920ns
tD(RUN-PWML)Delay from RUN high to PWML highVS13 > 11 V1.924.77.43µs
tON(MIN)Minimum on-time of PWML in LPMVSET = 5 V, IFB = -85 µA, VCS = 1 V

68

105

180

ns

PWMH
VPWMHHPWMH pin high-levelIPWMH = -1 mA4.394.664.83V
VPWMHLPWMH pin low-levelIPWMH = 1 mA

0.1

0.198

0.21

V

ISRC(PWMH)PWMH peak source currentVPWMH = 2.5 V16.52126.2mA
VPWMH = 3.5 V3.867.6mA
tR(PWMH)Turn-on rise time of PWMH pin, 10 % to 90 %CLOAD = 10 pF

8

24

ns

tF(PWMH)Turn-off fall time of PWMH pin, 90 % to 10 %CLOAD = 10 pF2229ns
tD(VS-PWMH)Dead time between VS high and PWMH 10 % high101828ns
PROTECTION
VOVPOver-voltage thresholdVVS increasing4.44.554.67V
VOCPOver-current thresholdVCS increasing1.141.221.27V
KOPP-PPLRatio of over-power threshold to peak-power thresholdVCST(OPP) / VCST(MAX) , and VCST(OPP)_LV / VCST(MAX)_LV0.720.750.78V/V
IVSL(RUN)VS line-sense run currentCurrent out of VS pin increasing313365408.6µA
IVSL(STOP)VS line-sense stop currentCurrent out of VS pin decreasing255305336.4µA
KVSLVS line sense ratioIVSL(STOP) / IVSL(RUN)0.720.8360.9A/A
RRDM(TH)RRDM threshold for CS pin fault355570kΩ
TJ(STOP)(1)Thermal-shutdown temperatureInternal junction temperature125162°C
tOPPOPP fault timerIFB = 0 A130164210ms
tBOBrown-out detection delay timeIVSL < IVSL(STOP)28.85585.2ms
tCSF1Maximum PWML on-time for detecting CS pin faultVSET = 5 V1.62.052.5µs
tCSF0Maximum PWML on-time for detecting CS pin faultRRDM < RRDM(TH) for VSET = 0 V0.851.051.27µs
tFDRFault reset delay timerOCP, OPP, OVP, SCP or CS pin fault

1.2

1.5

2.4

s

FLT INPUT
VNTCTHNTC shut-down voltageFLT voltage decreasing0.470.50.52V
RNTCTHNTC shut-down resistanceRNTC decreasing8.99.9111.18kΩ
RNTCRNTC recovery resistanceRNTC increasing21.22326.4kΩ
IFLTInput bias current for VFLT at VIOVPTHVFLT = 4.5 V-0.100.1µA
VIOVPTHShut-down voltage of input OVPFLT voltage increasing4.34.54.67V
VIOVPRHysteresis of input OVPFLT voltage increasing57.77487mV
tFLT(NTC)Delay time of NTC fault1450

100

µs
tFLT(IOVP)Delay time of input OVP fault555750917µs
VFLTZClamp voltage of FLT pinIFLT = 150 µA5.085.55.61V
RTZ INPUT
KTZtZ compensation ratioratio of tZ at IVSL = -200 µA to tZ at IVSL = -733 µA1.271.411.54s/s
tZ(MAX)Maximum programmable dead time from PWMH low to PWML highRRTZ = 280 kΩ, IVSL = -1 mA, VSET = 5 V397.8478592.8ns
tZ(MIN)Minimum programmable dead time from PWMH low to PWML highRRTZ = 78.4 kΩ, IVSL = -1 mA, VSET = 0 V56.17089.1ns
tZDead time from PWMH low to PWML highIVSL = -200 µA152.2175212.7ns
IVSL = -450 µA129.2150190ns
IVSL = -733 µA109.7125147.2ns
SWS INPUT
VTH(SWS)SWS zero voltage thresholdVSET = 5 V8.18.59.1V
VSET = 0 V3.74.044.4V
tD(SWS-PWML)Time between SWS low to PWML 10 % highVSWS step from 5 V to 0 V11.41726ns
FB INPUT
IFB(SBP)Maximum control FB currentIFB increasing64.27587.1µA
VFB(REG)Regulated FB voltage level4.024.254.53V
RFBIFB input resistance7.48.39.6kΩ
dICOMP/dt(1)Slope of internal ramp compensation current0.1920.2140.236A/s
ICOMPMagnitude of internal ramp compensation current46.758µA
RDM INPUT
tDM(MAX)Maximum PWMH width with maximum tuningVSWS = 12 V6.06.957.53µs
tDM(MIN)Minimum PWMH width with minimum tuningVSWS = 0 V3.03.433.77µs
XCD INPUT
VXCD(LR)XCD lower zero-crossing threshold5.96.627.2V
VXCD(UP)XCD upper zero-crossing threshold6.87.57.9V
IXCD(0)Leakage current in XCD wait stateVXCD = 15 V0.31.7µA
IXCD(1)First-step XCD sense currentVXCD = 15 V0.320.40.46mA
IXCD(2)Second-step XCD sense currentVXCD = 15 V0.610.7750.91mA
IXCD(3)Third-step XCD sense currentVXCD = 15 V0.731.151.6mA
IXCD(4)Fourth-step XCD sense currentVXCD = 15 V1.21.531.81mA
IXCD(MAX)Maximum XCD discharge currentVXCD = 15 V1.6522.5mA
VXCD(OVP)Clamp voltage of XCD OVPIXCD = 20 mA232630V
tXCD(STEP)Dwell time for each XCD sense step91214.6ms
tXCD(MAX)Maximum XCD discharge time230.4300373.3ms
tXCD(WAIT)XCD wait time7001071ms
(1) Ensured by design, not tested in production