SLUSEI6 November   2021 UCC28781-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Over Voltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RTW Package, 24-Pin WQFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
FLT 1 I The controller enters into the fault state if the FLT-pin voltage is pulled above 4.5 V or below 0.5 V. A 50-µA current source interfaces directly with an external NTC (negative temperature coefficient) thermistor to AGND pin for remote temperature sensing. The current source is active during the run state and inactive during the wait state. A 50-µs fault delay allows a filter capacitor to be placed on the FLT pin without false triggering the 0.5-V OTP fault when the controller enters into a run state from a wait state. Alternatively, a high-resistance voltage divider can be used to sense the bulk input capacitor voltage for line-OVP detection, and a 750-µs fault delay helps to prevent false triggering the 4.5-V input line-OVP from a short-duration bulk capacitor voltage overshoot during line surge and ESD strike events. When FLT-pin voltage is used for line-OVP detection, the external OTP can be implemented on CS pin.
RTZ 2 I A resistor between this pin and AGND pin programs an adaptive delay for transition to zero voltage from the turn-off edge of the PWMH signal to the turn-on edge of the PWML signal. Parasitic capacitance between this pin and any other net, including AGND, must be minimized to avoid noise coupling and its effect on the dead-time calculation.
RDM 3 I A resistor between this pin and AGND pin programs a synthesized demagnetization time used to control the on-time of the PWMH signal to achieve zero voltage switching on the primary switch. The controller applies a voltage on this pin that varies with the output voltage derived from the VS pin signal. Parasitic capacitance between this pin and any other net, including AGND, must be minimized to avoid noise coupling and its effect on the internal PWMH on-time calculation.
IPC 4 I This pin is an intelligent power control (IPC) pin to optimize the converter efficiency. A 50-µA current source directly interfaces with a resistor (RIPC) to AGND pin to program an increase in the peak current level at very light load; the burst frequency can be further reduced, helping to achieve low standby power and tiny-load power. If the IPC pin is connected to AGND without RIPC, the peak current level in very light load is set to a minimum level for the output ripple or audible noise sensitive designs. RIPC can also be connected between this pin and the CS pin or IPC pin can be directly connected to CS pin, so the 50-µA IPC current can create an output voltage dependent offset voltage on the CS pin for reducing output ripple in adaptive burst mode and improving light-load efficiency at lower output voltage level of a wide output voltage range design.
BUR 5 I This pin is used to program the burst threshold of the converter at light load. A resistor divider between REF and AGND is used to set a voltage at BUR to determine the peak current level when the converter enters adaptive burst mode (ABM). In addition, the Thevenin resistance on BUR is used to activate offset voltages for smooth mode transitions. A 2.7-µA pull up current increases the peak current threshold when the converter enters low-power mode (LPM) from ABM. A 5-µA pull down current reduces the peak current threshold when the converter enters into high-power mode (adaptive amplitude modulation, AAM) from ABM.
FB 6 I A current signal is coupled to this pin to close the converter regulation feedback loop. This pin presents a 4.25-V output that is designed to have 0-µA to 75-µA current pulled out of the pin corresponding to the converter operating from full-power to zero-power conditions. A 220-pF filter capacitor between FB pin and REF pin is recommended to desensitize the feedback signal from noise interference.
REF 7 O This pin is a 5-V reference output that requires a 0.22-µF ceramic bypass capacitor to the AGND pin. This reference is used to power internal circuits and can supply a limited external load current. Pulling this pin low shuts down PWM action and initiates a VDD restart.
AGND 8 G Analog ground and the ground return of PWMH and RUN drivers. Return all analog control signals to this ground.
CS 9 I This is the current-sense input pin. This pin couples to the current-sense resistor through a line-compensation resistor to control the peak primary current in each switching cycle. An internal current source on this pin, proportional to the converter’s input voltage, creates an offset voltage across the line-compensation resistor to balance the over-power protection (OPP) threshold level across input line. The CS pin can also provide an alternative OTP function, when the FLT pin is being used for the line input-OVP. A small-signal diode in series with an NTC resistor is connected between PWMH pin and CS pin to form the OTP detection. When PWMH is high, the NTC resistor and the line-compensation resistor become a resistor divider from 5 V and creates a temperature dependent voltage on CS pin. When CS pin voltage is higher than 1.2 V in PWMH on state for 2 consecutive cycles, the OTP fault on CS pin is triggered.
RUN 10 O This output pin is high when the controller is in the run state. This output is low during start-up, wait, and fault states. A 2.2-µs timer delays the initiation of PWML switching after this pin has gone high and S13-pin voltage is above its 10-V power-good threshold. The pull-up driving capability of both RUN and PWMH pins allows bias power management of a digital isolator through a common-cathode small-signal diode, so the power consumption can be reduced in the wait state.
PGND 11 G Low-side ground return of the PWML driver to the primary switch. The internal level shifter allows the common return impedance to be eliminated and improves higher frequency operation by decoupling the additional voltage spike on the current-sense resistor and layout parasitic inductance of the gate driving loop. For a silicon (Si) power FET, this pin can be connected to the source for a smaller gate driving loop. For a GaN power IC with a logic PWM input, this pin can be connected to AGND.

For a GaN-based gate-injection transistor (GIT), this pin can be directly connected to the separate source pin of a GIT GaN device, which enhances the turn-off speed.
PWML 12 O Primary switch gate driver output. The high-current capability (-0.5A/+1.9A) of PWML enables driving of a silicon power MOSFET with higher capacitive loading, a GIT GaN with continuous on-state current, or a GaN power IC with logic input. The maximum voltage level of PWML is clamped to the P13 pin voltage.
S13 13 O S13 is a switched bias-voltage source coupled to P13 through an internal 2.8-Ω switch controlled by the RUN pin. When RUN is high, the S13 decoupling capacitor is charged up to 13 V by an internal current limiter. The S13 pin voltage must increase above 10 V to initiate PWML switching. When RUN is low, S13 is discharged by its load. The power-on delay of any device powered by S13 must be less than 2 µs to be responsive to PWML. A 22-nF ceramic capacitor between S13 and the driver ground is recommended. S13 can also perform power management on a PFC controller at the same time through a diode, such that PFC can be disabled at very light-load condition.
P13 14 O P13 is a regulated 13-V bias-voltage source derived from VVDD. During VVDD startup, P13 pin is connected to the VDD pin internally, so an external high-voltage depletion MOSFET, such as BSS126, can provide controlled startup current to charge the VDD capacitor. After the initial startup, P13 recovers back to 13-V regulation. A 1-µF ceramic bypass capacitor is required from P13 to AGND. A 20-V Zener diode between P13 and AGND is recommended to protect this pin from overstress, such as if the connection between this pin and the depletion MOSFET gate is fail-open or if line surge energy is coupled to this pin.
PWMH 15 O PWM output signal used to control the gate of a secondary-side synchronous rectifier (SR) MOSFET through an external isolating gate driver. The driving capability is designed to bias a level-shifting isolator through a small-signal diode, or can also transmit the signal to secondary-side driving circuitry through a pulse transformer. The maximum voltage level of PWMH is clamped to REF.
SWS 16 I This sensing input is used to monitor the switch-node voltage as it nears zero volts in normal operation for ZVS auto-tuning. The source of a high-voltage depletion-mode MOSFET, such as BSS126, is coupled to this pin through a current-limiting resistor so only the useful switching characteristic below 15 V is monitored. During start-up, this pin is connected to the VDD pin internally to allow the depletion-mode MOSFET to provide start-up current. The external current-limit resistor and a small bidirectional TVS across gate and source should be added to protect the VGS from potential abnormal voltage stress. The resistor should be higher than 500 Ω and less than 820 Ω. The clamping voltage of TVS should be less than the MOSFET voltage rating but greater than 15 V. Moreover, the resistor and a 22-pF ceramic capacitor between the SWS pin and the bulk input capacitor ground form a small sensing delay to help the internal detection circuit to identify the ZVS characteristic correctly.
XCD 17, 18 I X-cap Discharge input pins with 2-mA maximum discharge current capability. A line zero-crossing (LZC) threshold of 6.5 V on XCD is used to detect AC-line presence. When LZC is not detected within an 84-ms test period, the discharge current is enabled for a maximum period of 300 ms followed by a no-current blanking time of 700 ms. When AC-line recovers and LZC is detected again, the controller can reset the fault state almost immediately and will attempt to restart without waiting to fully discharge the bulk input capacitor. For the auto-recovery fault protections, if the controller is in 1.5-s auto-recovery fault state, LZC can reset the timer and speed up the restart attempt. The two redundant XCD pins help to provide the X-cap discharge function even when one pin is in fail-open condition. To form the discharge path, an anode of two high-voltage diode rectifiers is connected to each X-cap terminal, the two diode cathodes are connected together to a 26-kΩ high-voltage current-limiting resistance, and the drain-to-source connection of a high-voltage depletion MOSFET couples the resistance to the XCD pins. Two series 13-kΩ SMD resistors in 1206 size can be used as the current limiting device, and share the potential transient voltage from the AC-line. A 600-V rated MOSFET such as BSS126 is needed as the high voltage blocking device. The MOSFET gate is connected to the P13 pin, so the XCD pins can obtain enough signal headroom for LZC detection. If the X-cap discharge function is not needed, XCD pins must be connected to AGND pin to disable the function, and the diode-resistor-MOSFET path must be removed.
VDD 19 P Controller bias power input. A ceramic capacitor with 10-µF or 15-µF capacitance is recommended, and the minimum voltage rating is 25 V.
GTP1 20 G Ground This Pin. This pin must be connected to AGND for proper operation of the device.
GTP2 21 G Ground This Pin. This pin must be connected to AGND for proper operation of the device.
GTP3 22 G Ground This Pin. This pin must be connected to AGND for proper operation of the device.
VS 23 I This voltage-sensing input pin is coupled to an auxiliary winding of the converter’s transformer via a resistor divider. The pin and associated external resistors are used to monitor the output and input voltages and switching edges of the converter at different moments within each switching cycle. Parasitic capacitance between VS and any net, including AGND, must be minimized to avoid adverse effects on output voltage sensing, edge detection, and the dead-time calculation.
SET 24 I This pin is used to configure the controller to be optimized for gallium nitride (GaN) power FETs or silicon (Si) power FETs on the primary side. Depending on the setting, it will optimize parameters of the ZVS control loop, dead-time adjustment, and protection features. When pulled high to REF pin, it is optimized for Si FETs. When pulled low to AGND, it is optimized for GaN FETs.
Thermal Pad G The thermal pad (TP) must be connected to AGND.
(1) I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power