SLUSEQ9D July   2022  – April 2024 TPS1211-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS12111-Q1 Only)
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection with Auto-Retry
        2. 8.3.3.2 Overcurrent Protection with Latch-Off
        3. 8.3.3.3 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
      6. 8.3.6 Remote Temperature Sensing and Protection (DIODE)
      7. 8.3.7 Output Reverse Polarity Protection
      8. 8.3.8 TPS1211x-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving Zonal Controller Loads on 12-V Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Reverse Polarity Protection with TPS12110-Q1
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.3.2 External Component Selection

By following similar design procedure as outlined in Detailed Design Procedure, the external component values are calculated as below:

  • RSNS = 1 mΩ.

  • RSET = 100 Ω.

  • RIWRN = 49.9 kΩ to set 24 A as overcurrent protection threshold.

  • RISCP = 1.468 kΩ to set 30 A as short-circuit protection threshold.

  • CTMR = 68 nF to set 1-ms over current protection time.

  • R1 , R2 and R3 are selected as 390 kΩ, 71.5 kΩ and 15.8 kΩ respectively to set VIN undervoltage lockout threshold at 6.5 V and overvoltage cutoff threshold at 36 V.
  • RIMON = 15 kΩ to limit maximum V(IMON) voltage to 3.3 V at full-load current of 24 A.
  • To reduce conduction losses, BUK7S0R5-40HJ MOSFET is selected. Two FETs are used in back-to-back configuration for reverse current blocking.
    • 40-V VDS(MAX) and 20-V VGS(MAX).
    • RDS(ON) is 0.47-mΩ typical at 10-V VGS.
    • Qg of each MOSFET is 190 nC.
  • CBST = (2 × Qg) / 1 V = 380 nF; Choose the closest available standard value: 470 nF, 10 %.
  • Q4 selection: Any signal N-MOSFET with 40-V VDS support is sufficient. DMN601WKQ-7 is selected for the current design and a 12-V Zener diode SZMM3Z12VST1G is used for VGS protection.