SLUSEQ9D July 2022 – April 2024 TPS1211-Q1
PRODUCTION DATA
The recommended range of the overcurrent protection threshold voltage, V(SNS_WRN), extends from 10 mV to 200 mV. Values near the low threshold of 10 mV can be affected by the system noise. Values near the upper threshold of 200 mV can cause high power dissipation in the current sense resistor. To minimize both the concerns, 25 mV is selected as the overcurrent protection threshold voltage. Use the following equation to calculate the current sense resistor, RSNS.
The next smaller available sense resistor 800 μΩ, 1% is chosen.
To improve signal to noise ratio or for better overcurrent protection accuracy, higher overcurrent protection threshold voltage, V(SNS_WRN) can be selected.
RSET is the resistor connected between VS and CS+ pins. This resistor scales the overcurrent protection threshold voltage and coordinates with RIWRN and RIMON to determine the overcurrent protection threshold and current monitoring output. The recommended range of RSET is 50 Ω – 100 Ω.
RSET is selected as 100 Ω, 1% for this design example.
The RIWRN sets the overcurrent protection threshold, whose value can be calculated using Equation 15.
To set 30 A as overcurrent protection threshold, RIWRN value is calculated to be 49.5 kΩ.
Choose the closest available standard value: 49.9 kΩ, 1%
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The RISCP sets the short-circuit protection threshold. Use the following equation to calculate the value.
To set 35 A as short-circuit protection threshold, RISCP value is calculated to be 1.19 kΩ.
Choose the closest available standard value: 1.2 kΩ, 1%.
In case where large di/dt is involved, the system and layout parasitic inductances can generate large differential signal voltages between ISCP and CS– pins. This action can trigger false short-circuit protection and nuisance trips in the system. To overcome such scenario, TI recommends to add filter capacitor of 1 nF across ISCP and CS– pins close to the device. Because nuisance trips are dependent on the system and layout parasitics, TI recommends to test the design in a real system and tweaked as necessary.
For the design example under discussion, overcurrent transients are allowed for 1-ms duration. This blanking interval, tOC can be set by selecting appropriate capacitor CTMR from TMR pin to ground. Use the following equation to calculate the value of CTMR to set 1 ms for tOC.
Choose closest available standard value: 68 nF, 10%.
For selecting the MOSFET Q1, important electrical parameters are the maximum continuous drain current ID, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), and the drain-to-source ON-resistance RDSON.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current.
The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest voltage seen in the application. Considering 35 V as the maximum application voltage, MOSFETs with VDS voltage rating of 40 V is suitable for this application.
The maximum VGS TPS1211-Q1 can drive is 13 V, so a MOSFET with 15-V minimum VGS rating must be selected.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred.
Based on the design requirements, BUK7S0R5-40HJ is selected and its ratings are:
40-V VDS(MAX) and 20-V VGS(MAX)
RDS(ON) is 0.47-mΩ typical at 10-V VGS
MOSFET Qg(total) is 190 nC
The internal charge pump charges the external bootstrap capacitor (connected between BST and SRC pins) with approximately 100 μA. Use the following equation to calculate the minimum required value of the bootstrap capacitor for driving two parallel BUK7S0R5-40HJ MOSFETs.
Choose closest available standard value: 470 nF, 10 %.
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider network of R1 and R2 connected between VS, EN/UVLO and GND pins of the device. The values required for setting the undervoltage and overvoltage are calculated by solving Equation 19.
For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance for R1 and R2. However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I(R12) must be chosen to be 20 times greater than the leakage current of UVLO pin.
From the device electrical specifications, V(UVLOR) = 1.18 V. From the design requirements, VINUVLO is 6.5 V. To solve the equation, first choose the value of R1 = 470 kΩ and use Equation 19 to solve for R2 = 104.24 kΩ. Choose the closest standard 1% resistor values: R1 = 470 kΩ, and R2 = 105 kΩ.
For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on the gate (G) of the precharge FET Q3. The target inrush current to charge 1 mF of output capacitance to 12-V in 10 ms can be estimated by Equation 20. The required gate capacitance Cg to limit the inrush current to 1.2 A can be calculated by using , where I(G) = 100 μA (typical) is the gate charging current of pin 'G'. By solving , we get Cg as 83.33 nF.
Choose the closest available standard value: 82 nF, 10%.
A series resistor Rg must be used in conjunction with Cg to limit the discharge current from Cg during turn-off and to stabilize the gate 'G' during slew rate control. The recommended value for Rg is between 220 Ω to 470 Ω.
Voltage at IMON pin V(IMON) is proportional to the output load current. This can be connected to an ADC of the downstream system for monitoring the operating condition and health of the system. The RIMON must be selected based on the maximum load current and the input voltage range of the ADC used. RIMON is set using Equation 22.
Where VSNS = IOC × RSNS and V(OS_SET) is the input referred offset (± 200 µV) of the current sense amplifier.
The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(VS) – 0.5V], 5.5V) to ensure linear output. This puts a limitation on the maximum value of RIMON resistor. The IMON pin has an internal clamp of 6.5 V (typical).
For IOC = 30 A and considering the operating range of ADC to be 0 V to 3.3 V (for example, V(IMON) = 3.3 V), RIMON can be calculated as
Selecting RIMON value less than shown in Equation 23 ensures that ADC limits are not exceeded for maximum value of load current. Choose the closest available standard value: 16.5 kΩ, 1%.