SLUSEQ9D July 2022 – April 2024 TPS1211-Q1
PRODUCTION DATA
Connect a resistor, RISCP, as shown in Figure 8-14.
Use Equation 10 to calculate the required RISCP value.
Where, RSNS is the current sense resistor, and ISC is the desired short-circuit protection level. After the current exceeds the ISC threshold then, PD pulls low to SRC within 1.2 µs in TPS12111-Q1, TPS12112-Q1 and 4 µs in TPS12110-Q1, protecting the FET. FLT_I asserts low at the same time. Subsequent to this event, the charge and discharge cycles of CTMR starts similar to the behavior post FET OFF event in the over current protection scheme.
Latch-off can also achieved in the similar way as explained in the overcurrent protection scheme.