SLUSET8B October   2023  – June 2024 TPSM843620

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Module)
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VIN Pins and VIN UVLO
      2. 6.3.2  Enable and Adjustable UVLO
      3. 6.3.3  Adjusting the Output Voltage
      4. 6.3.4  Switching Frequency Selection
      5. 6.3.5  Switching Frequency Synchronization to an External Clock
        1. 6.3.5.1 Internal PWM Oscillator Frequency
        2. 6.3.5.2 Loss of Synchronization
        3. 6.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 6.3.6  Ramp Amplitude Selection
      7. 6.3.7  Soft Start and Prebiased Output Start-Up
      8. 6.3.8  Mode Pin
      9. 6.3.9  Power Good (PGOOD)
      10. 6.3.10 Current Protection
        1. 6.3.10.1 Positive Inductor Current Protection
        2. 6.3.10.2 Negative Inductor Current Protection
      11. 6.3.11 Output Overvoltage and Undervoltage Protection
      12. 6.3.12 Overtemperature Protection
      13. 6.3.13 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Discontinuous Conduction Mode During Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 1.0V Output, 1MHz Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Switching Frequency
          2. 7.2.1.2.2  Output Inductor Selection
          3. 7.2.1.2.3  Output Capacitor
          4. 7.2.1.2.4  Input Capacitor
          5. 7.2.1.2.5  Adjustable Undervoltage Lockout
          6. 7.2.1.2.6  Output Voltage Resistors Selection
          7. 7.2.1.2.7  Bootstrap Capacitor Selection
          8. 7.2.1.2.8  BP5 Capacitor Selection
          9. 7.2.1.2.9  PGOOD Pullup Resistor
          10. 7.2.1.2.10 Current Limit Selection
          11. 7.2.1.2.11 Soft-Start Time Selection
          12. 7.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 7.2.1.2.13 MODE Pin
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
7.2.1.2.3 Output Capacitor

The output voltage ripple and how the regulator responds to a large change in load current are the two primary considerations for selecting the value of the output capacitor. The output capacitance must be selected based on the more stringent of these criteria.

The desired response to a large change in the load current is the first criteria and is typically the most stringent. A regulator does not respond immediately to a large, fast increase or decrease in load current. The output capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop must sense the change in the output voltage then adjust the peak switch current in response to the change in load. The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically the loop bandwidth is near fSW / 10. Equation 6 estimates the minimum output capacitance necessary, where ΔIOUT is the change in output current and ΔVOUT is the allowable change in the output voltage.

For this example, the transient load response is specified as a 3% change in VOUT for a load step of 3A. Therefore, ΔIOUT is 3A and ΔVOUT is 30mV. Using this target gives a minimum capacitance of 159μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be considered for load step response.

Equation 6. TPSM843620

In addition to the loop bandwidth, the inductor current slew rate limiting how quickly the regulator responds to the load step is possible. For low duty cycle applications, the time the inductor current takes to ramp down after a load step down can be the limiting factor. Equation 7 estimates the minimum output capacitance necessary to limit the change in the output voltage after a load step down. Using the 0.47µH inductance selected gives a minimum capacitance of 70.5µF.

Equation 7. TPSM843620

Equation 8 calculates the minimum output capacitance needed to meet the output voltage ripple specification. In this case, the target maximum steady state output voltage ripple is 10mV. Under this requirement, Equation 8 yields 30µF.

Equation 8. TPSM843620

where

  • ΔIOUT is the change in output current
  • ΔVOUT is the allowable change in the output voltage
  • fsw is the regulators switching frequency
  • Voripple is the maximum allowable steady state output voltage ripple
  • Iripple is the inductor ripple current

Lastly, if an application does not have a strict load transient response or output ripple requirement, a minimum amount of capacitance is still required to make sure the control loop is stable with the lowest gain ramp setting on the MODE pin. Equation 9 estimates the minimum capacitance needed for loop stability. This equation sets the minimum amount of capacitance by keeping the LC frequency relative to the switching frequency at a minimum value. See Figure 7-3 for the limit versus output voltage with the lowest gain ramp setting of 1pF. With a 1V output, the minimum ratio is 35 and with this ratio, Equation 9 gives a minimum capacitance of 66 µF.

Equation 9. TPSM843620

Equation 10 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple specification and this shows the ESR must be less than 6mΩ. In this case, ceramic capacitors are used and the combined ESR of the ceramic capacitors in parallel is much less than is needed to meet the ripple. Capacitors also have limits to the amount of ripple current capacitors can handle without producing excess heat and failing. An output capacitor that can support the inductor ripple current must be specified. The capacitor data sheet specifies the RMS value of the maximum ripple current. Equation 11 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 11 yields 580mA and ceramic capacitors typically have a ripple current rating much higher than this.

Equation 10. TPSM843620

Equation 11. TPSM843620

Select X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer website. For this application example, one 47µF, 10V, X5R, 0805 and three 100µF, 10V, X5R, 1206 ceramic capacitors each with 2mΩ of ESR are used. The one 47µF capacitor is used because the 47µF capacitor has a higher resonance frequency and can help reduce the output ripple caused by parasitic inductance. With the four parallel capacitors, the estimated effective output capacitance after derating using the capacitor manufacturer website is 327µF. There is about a –7% DC bias derating at 1V. This design was able to use less than the calculated minimum because the loop crossover frequency was above the fSW / 10 estimate as shown in the Load Transient graph in the Application Curves.