SLUSF62 April   2024 TPS53840

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Device and Documentation Support
    1. 4.1 Receiving Notification of Documentation Updates
    2. 4.2 Support Resources
    3. 4.3 Trademarks
    4. 4.4 Electrostatic Discharge Caution
    5. 4.5 Glossary
  6. 5Revision History
  7. 6Mechanical, Packaging, and Orderable Information
    1. 6.1 Packaging Information
    2. 6.2 Tape and Reel Information
    3.     15

1 Features

  • Compliant to JEDEC PMIC5020 for DDR5 MRDIMM and RDIMM
  • 4 Buck regulators
    • SWA (1.1V) 8.5A DC/10A Pk
    • SWB (1.1V) 8.5A DC/10A Pk
    • SWC (1.1V) 10A DC/11.5A Pk
    • SWD (1.8V) 3A DC/3.5A Pk
  • Single or dual phase for SWA and SWB
  • 2 LDO: 1.8V / 25mA and 1.0V / 20mA
  • VIN_Bulk (4.25V to 15V) and VIN_Mgmt (3.0V to 3.6V) input supplies
  • Automatic switchover from VIN_Mgmt to VIN_Bulk
  • Overvoltage, under voltage, over current, temperature warning and temperature shutdown
  • Error injection capability
  • DIMM specific registers for customization (EEPROM)
  • Persistent error log registers
  • Programmable switching frequency: 500kHz to 1.375MHz
  • Power good pin (CAMP) and General status interrupt pin (GSI_n)
  • I2C and I3C Bus interface for telemetry of voltage, current, power, temperature, and fault conditions
  • Enable with I2C/I3C, VR_EN pin or Auto power on
  • 5mm Ă— 5mm, 35-Pin, QFN PowerPad™ package