SLUSFB5
June 2024
BQ41Z50
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Description (continued)
5
Pin Configuration and Functions
5.1
Pin Equivalent Diagrams
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Supply Current
6.6
Power Supply Control
6.7
Current Wake Detector
6.8
VC0, VC1, VC2, VC3, VC4, PACK
6.9
SMBD, SMBC
6.10
PRES/SHUTDN, DISP
6.11
ALERT
6.12
Coulomb Counter Digital Filter (CC1)
6.13
ADC Digital Filter
6.14
CHG, DSG High-side NFET Drivers
6.15
Precharge (PCHG) FET Drive
6.16
FUSE Drive
6.17
Internal Temperature Sensor
6.18
TS1, TS2, TS3, TS4
6.19
Flash Memory
6.20
GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7
6.21
Elliptical Curve Cryptography (ECC)
6.22
SMBus Interface Timing
6.23
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Primary (1st Level) Safety Features
7.3.2
Secondary (2nd Level) Safety Features
7.3.3
Charge Control Features
7.3.4
Gas Gauging
7.3.5
Lifetime Data Logging Features
7.3.6
Authentication
7.3.7
Configuration
7.3.7.1
Oscillator Function
7.3.7.2
Real Time Clock
7.3.7.3
System Present Operation
7.3.7.4
Emergency Shutdown
7.3.7.5
2-Series, 3-Series, or 4-Series Cell Configuration
7.3.7.6
Cell Balancing
7.3.7.7
LED Display
7.3.8
Battery Parameter Measurements
7.3.8.1
Charge and Discharge Counting
7.3.8.2
Voltage
7.3.8.3
Current
7.3.8.4
Temperature
7.3.8.5
Communications
7.3.8.5.1
SMBus On and Off State
7.4
Device Functional Modes
8
Applications and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
High-Current Path
8.2.2.1.1
Protection FETs
8.2.2.1.2
Chemical Fuse
8.2.2.1.3
Lithium-Ion Cell Connections
8.2.2.1.4
Sense Resistor
8.2.2.1.5
ESD Mitigation
8.2.2.2
Gas Gauge Circuit
8.2.2.2.1
Coulomb-Counting Interface
8.2.2.2.2
Low-dropout Regulators (LDOs)
8.2.2.2.2.1
REG18
8.2.2.2.2.2
REG135
8.2.2.2.3
System Present
8.2.2.2.4
SMBus Communication
8.2.2.2.5
FUSE Circuitry
8.2.2.3
Secondary-Current Protection
8.2.2.3.1
Cell and Battery Inputs
8.2.2.3.2
External Cell Balancing
8.2.2.3.3
PACK and FET Control
8.2.2.3.4
Temperature Measurement
8.2.2.3.5
LEDs
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
Protector FET Bypass and Pack Terminal Bypass Capacitors
8.4.1.2
ESD Spark Gap
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Third-Party Products Disclaimer
9.2
Documentation Support
9.2.1
Related Documentation
9.3
Receiving Notification of Documentation Updates
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
1
Features
Fully integrated 2-series, 3-series, and 4-series cell Li-ion, LiPO, or LiFePO
4
battery pack manager and protection
Ultra-low power 32-bit RISC processor
TI
Dynamic Z-Trackā¢
algorithm
Up to 40V tolerant power supply pins
High side N-CH protection FET drive with configurable drive strength
Precision analog front-end with two independent 16-bit ADCs:
Support for simultaneous current and voltage sampling
Support for up to four external thermistor measurements and an internal temperature sensor
Primary and secondary levels of protection
Overvoltage and undervoltage
Overcurrent in charge and discharge
Short circuit in discharge
Overtemperature
Charge timeout
CHG and DSG FET drivers
Sophisticated charge algorithms
JEITA
Adaptive charging based on cycle time, run time, and SOH
Cell balancing
Integrated cell balancing while charging or at rest
Supports TURBO mode
Diagnostic lifetime data monitor and black box recorder
Optional up to three LED display support
Supports SHA-1, SHA-2, and Elliptic Curve Cryptography (ECC) authentication
Up to 1MHz SMBus v3.2 host communication support
Compact package: 32-lead WQFN (RSN)