SLUSFE4A January   2024  – June 2024 UCC21330

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Disable Response Time
    4. 6.4 Programmable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21330
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead-Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Gate to Source Resistor Selection
        5. 8.2.2.5 Estimate Gate Driver Power Loss
        6. 8.2.2.6 Estimating Junction Temperature
        7. 8.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.7.1 Selecting a VCCI Capacitor
          2. 8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.7.3 Select a VDDB Capacitor
        8. 8.2.2.8 Dead Time Setting Guidelines
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

5.8 Electrical Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitance from VCCI to GND, VVDDx = 12V (for 5V and 8V UVLO), 15V (for 12V UVLO), , 1-µF + 100-nF capacitance from VDDA and VDDB to VSSA and VSSB, DT pin floating, EN = VCC or DIS = GND, TJ = –40°C to +150°C,  CL = 0 pF, unless otherwise noted (1) 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCC VCC quiescent current VINx = 0 V, DIS = GND; VCC=3.3V 1.4 2 mA
VINx = 0 V, DIS = GND; VCC=5V 1.4 2
VINx = VCC, DIS = GND; VCC=3.3V 4.2 4.8
VINx = VCC, DIS = GND; VCC=5V 4.2 4.8
VINx PWM at 0V to VCC at fSW = 500kHz, DIS = GND; VCC=3.3V 2.7 3.2
VINx PWM at 0V to VCC at fSW = 500kHz, DIS = GND; VCC=5V 2.7 3.2
IVDDx VDDx quiescent current VINx = 0 V, DIS = GND 1.2 2 mA
VINx = 0 V, DIS = GND; VDD=25V 1.4 2.3
VINx = VCC, DIS = GND 1.4 2.2
VINx = VCC, DIS = GND; VDD=25V 1.5 2.5
VINx PWM at 0V to VCC at fSW = 500kHz, DIS = GND 2.7 4.4
VINx PWM at 0V to VCC at fSW = 500kHz, DIS = GND; VDD=25V 2.7 4.4
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCC_ON VCC UVLO Rising Threshold 2.55 2.7 2.85 V
VVCC_OFF VCC UVLO Falling Threshold 2.35 2.5 2.65
VVCC_HYS VCC UVLO Threshold Hysteresis 0.2
tVCC+ to OUT VCC UVLO ON Delay 18 42 80 µs
tVCC– to OUT VCC UVLO OFF Delay 0.5 1.2 7
tVCCFIL VCC UVLO Deglitch Filter 0.4 0.9 3.1
VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS AND DELAY
VVDD_ON VDDx UVLO Rising Threshold 5-V UVLO Option 5.7 6.0 6.3 V
VVDD_OFF VDDx UVLO Falling Threshold 5.4 5.7 6.0
VVDD_HYS VDDx UVLO Threshold Hysteresis 0.30
VVDD_ON VDDx UVLO Rising Threshold 8-V UVLO Option 7.7 8.5 8.9 V
VVDD_OFF VDDx UVLO Falling Threshold 7.2 7.9 8.4
VVDD_HYS VDDx UVLO Threshold Hysteresis 0.6
VVDD_ON VDDx UVLO Rising Threshold 12-V UVLO Option (Metal Option) 11.7 12.5 13.3 V
VVDD_OFF VDDx UVLO Falling Threshold 10.7 11.5 12.3
VVDD_HYS VDDx UVLO Threshold Hysteresis 1.0
tVDD+ to OUT VDDx UVLO ON Delay 10 µs
tVDD– to OUT VDDx UVLO OFF Delay 0.1 0.5 2
tVDDFIL VDDx UVLO Deglitch Filter 0.1 0.17
INA, INB, AND /DIS
VINx_H,
VDIS_H, 		Input High Threshold Voltage 2 2.3 V
VINx_L,
VDIS_L, 		Input Low Threshold Voltage 0.8 1
VINx_HYS,
VDIS_HYS, 		Input Threshold Hysteresis 1
RINxD INx Pin Pull Down Resistance INx = 3.3V 50 90 185 kΩ
RDISD DIS Pin Pull Up Resistance DIS= 3.3V 50 90 185 kΩ
OUTPUT DRIVER STAGE
IO+ Peak Output Source Current  CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz –4 A
IO– Peak Output Sink Current CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz 6 A
ROH Pull up resistance. ROH does not represent drive pull-up performance. See Section 8.3.4 for details. IOUTx = –0.05A 5 Ω
ROL Pull down resistance IOUTx = 0.05A 0.55
ACTIVE PULL-DOWN
VOUTPD Output Active Pull Down on OUTx IOUT = 200mA, VDDx floating and unpowered. 1.6 2 V
VOUTPD Output Active Pull Down on OUTx IOUT = 200mA, CVDD=100nF and unpowered. 1.6 2 V
DEADTIME AND OVERLAP PROGRAMMING
DTS Disable DT Function DT pin open or pull DT pin to VCC Output overlapping determined by INA, INB -
Deadtime Programming for RDT≤0.15kΩ RDT=0~0.15kΩ -6 0.2 6 ns
Deadtime Programming for 1.7kΩ≤RDT≤100kΩ
DT (ns) = 8.6×RDT(kΩ) + 13		 RDT = 10 kΩ 86 99 112 ns
RDT = 20 kΩ 167 185 203
RDT = 50 kΩ 399 443 487
(1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless
otherwise noted)