SLUSFF2 October   2024 UCG28826

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Detailed Pin Descriptions
      1. 6.3.1  HV - High Voltage Input
      2. 6.3.2  SW - Switch Node
      3. 6.3.3  GND – Ground Return
      4. 6.3.4  FLT - External Overtemperature Fault
      5. 6.3.5  FB ­­– Feedback
      6. 6.3.6  TR - Turns Ratio
      7. 6.3.7  IPK - Peak Current and Dithering
      8. 6.3.8  FCL - Frequency clamp and fault response
      9. 6.3.9  CDX - CCM, drive strength and X-cap discharge
      10. 6.3.10 VCC - Input Bias
    4. 6.4 Feature Description
      1. 6.4.1  Self Bias and Auxless Sensing
      2. 6.4.2  Control Law
        1. 6.4.2.1 Valley Switching
        2. 6.4.2.2 Frequency Foldback
        3. 6.4.2.3 Burst Mode
        4. 6.4.2.4 Continuous Conduction Mode (CCM)
      3. 6.4.3  GaN HEMT Switching Capability
      4. 6.4.4  Soft Start
      5. 6.4.5  Frequency Clamp
      6. 6.4.6  Frequency Dithering
      7. 6.4.7  Slew Rate Control
      8. 6.4.8  Transient Peak Power Capability
      9. 6.4.9  X-Cap Discharge
      10. 6.4.10 Fault Protections
        1. 6.4.10.1 Brownout Protection
        2. 6.4.10.2 Short-Circuit Protection
        3. 6.4.10.3 Output Over Voltage Protection
        4. 6.4.10.4 Over Power Protection (OPP, LPS)
        5. 6.4.10.5 Overtemperature Protection
        6. 6.4.10.6 Open FB Protection
        7. 6.4.10.7 Error Codes for Protections
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Bulk Capacitor
        2. 7.2.2.2 Transformer Primary Inductance and Turns Ratio
        3. 7.2.2.3 Output Capacitor
        4. 7.2.2.4 Selection Resistors
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
    2. 10.2 Mechanical Data

6.4.2.3 Burst Mode

If output power continues to reduce while in frequency foldback mode, the device enters burst mode when FB pin voltages reaches 0.25V for the first time and the device stops switching. Due to this, depending on the output power, once FB pin voltage recovers to 0.3V is when device resumes switching in burst mode.

The UCG28826's burst mode offers three 1st valley QR switching cycles followed by a min. 70μs delay before start of next burst packet. Valley switching reduces switching losses while the delay limits power delivery in burst mode and device transitions to other modes of operation at higher power to maintain high efficiency in the range of output power. In burst mode, frequency clamp is fixed at 250kHz and primary GaN HEMT turns on at next valley after expiration of clamp timer. With this, switching losses are kept low with valley switching with limit on electromagnetic emissions with minimum peak current to pass emission standards. Burst mode switching waveforms are shown in Figure 6-7.

UCG28826 Burst Mode Entry and Exit Waveforms Figure 6-7 Burst Mode Entry and Exit Waveforms