SLUSFL6A June   2024  – November 2024 TPSM82866C

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
      2. 7.3.2 Forced PWM Mode
      3. 7.3.3 Optimized Transient Performance from PWM to PSM Operation
      4. 7.3.4 Low Dropout Operation (100% Duty Cycle)
      5. 7.3.5 Enable and Soft-Start Ramp
      6. 7.3.6 Switch Current Limit and HICCUP Short-Circuit Protection
      7. 7.3.7 Undervoltage Lockout
      8. 7.3.8 Thermal Warning and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Output Discharge
      3. 7.4.3 Start-Up Output Voltage and I2C Target Address Selection (VSET)
      4. 7.4.4 Select Output Voltage Registers (VID)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-Mode, Fast-Mode, and Fast-Mode Plus Protocol
      3. 7.5.3 HS-Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. 8 Register Map
    1. 8.1 Target Address Byte
    2. 8.2 Register Address Byte
    3. 8.3 VOUT Register 1
    4. 8.4 VOUT Register 2
    5. 8.5 CONTROL Register
    6. 8.6 STATUS Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input and Output Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6 I2C Interface Timing Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT
f(SCL) SCL clock frequency Standard mode 100 kHz
Fast mode 400 kHz
Fast mode plus 1 MHz
High-speed mode (write operation), CB – 100pF max 3.4 MHz
High-speed mode (read operation), CB – 100pF max 3.4 MHz
High-speed mode (write operation), CB – 400pF max 1.7 MHz
High-speed mode (read operation), CB – 400pF max 1.7 MHz
tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs
Fast mode 1.3 µs
Fast mode plus 0.5 µs
tHD, tSTA Hold time (repeated) START condition Standard mode 4 µs
Fast mode 600 ns
Fast mode plus 260 ns
High-speed mode 160 ns
tLOW LOW period of the SCL clock Standard mode 4.7 µs
Fast mode 1.3 µs
Fast mode plus 0.5 µs
High-speed mode, CB – 100pF max 160 ns
High-speed mode, CB – 400pF max 320 ns
tHIGH HIGH period of the SCL clock Standard mode 4 µs
Fast mode 600 ns
Fast mode plus 260 ns
High-speed mode, CB – 100pF max 60 ns
High-speed mode, CB – 400pF max 120 ns
tSU, tSTA Setup time for a repeated START condition Standard mode 4.7 µs
Fast mode 600 ns
Fast mode plus 260 ns
High-speed mode 160 ns
tSU, tDAT Data setup time Standard mode 250 ns
Fast mode 100 ns
Fast mode plus 50 ns
High-speed mode 10 ns
tHD, tDAT Data hold time Standard mode 0 3.45 µs
Fast mode 0 0.9 µs
Fast mode plus 0 µs
High-speed mode, CB – 100pF max 0 70 ns
High-speed mode, CB – 400pF max 0 150 ns
tRCL Rise time of SCL signal Standard mode 1000 ns
Fast mode 20 + 0.1 CB 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100pF max 10 40 ns
High-speed mode, CB – 400pF max 20 80 ns
tRCL1 Rise time of SCL signal after a repeated START condition and after an acknowledge BIT Standard mode 20 + 0.1 CB 1000 ns
Fast mode 20 + 0.1 CB 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100pF max 10 80 ns
High-speed mode, CB – 400pF max 20 160 ns
tFCL Fall time of SCL signal Standard mode 20 + 0.1 CB 300 ns
Fast mode 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100pF max 10 40 ns
High-speed mode, CB – 400pF max 20 80 ns
tRDA Rise time of SDA signal Standard mode 1000 ns
Fast mode 20 + 0.1 CB 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100pF max 10 80 ns
High-speed mode, CB – 400pF max 20 160 ns
tFDA Fall time of SDA signal Standard mode 300 ns
Fast mode 20 + 0.1 CB 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100pF max 10 80 ns
High-speed mode, CB – 400pF max 20 160 ns
tSU, tSTO Setup time of STOP condition Standard mode 4 µs
Fast mode 600 ns
Fast mode plus 260 ns
High-Speed mode 160 ns
CB Capacitive load for SDA and SCL Standard mode 400 pF
Fast mode 400 pF
Fast mode plus 550 pF
High-Speed mode 400 pF