RSVD (Bits 31–27):
Reserved |
|
|
|
DFW (Bit 26): Data Flash
Wearout Failure |
|
1 = |
Detected |
|
0 = |
Not Detected |
|
|
|
RSVD (Bit 25):
Reserved |
|
|
|
IFC (Bit 24): Instruction
Flash Checksum Failure |
|
1 = |
Detected |
|
0 = |
Not Detected |
|
|
|
RSVD (Bits
23–18):
Reserved |
|
|
|
DFETF (Bit 17): Discharge
FET Failure |
|
1 = |
Detected |
|
0 = |
Not Detected |
|
|
|
CFETF (Bit 16): Charge
FET Failure |
|
1 = |
Detected |
|
0 = |
Not Detected |
|
|
|
RSVD (Bits 15–13):
Reserved |
|
|
|
VIMR (Bit 12): Voltage
Imbalance While Pack Is At Rest Failure |
|
1 = |
Detected |
|
0 = |
Not Detected |
|
|
|
VIMA (Bit 11): Voltage
Imbalance While Pack Is Active Failure |
|
1 = |
Detected |
|
0 = |
Not Detected |
|
|
|
RSVD (Bits 10–2):
Reserved |
|
|
|
SOV (Bit 1): Safety Cell
Overvoltage Failure |
|
1 = |
Detected |
|
0 = |
Not Detected |
|
RSVD (Bit 0):
Reserved |