SLUUAQ3A April 2016 – October 2022 BQ4050
Class | Subclass | Name | Type | Min | Max | Default | Unit |
---|---|---|---|---|---|---|---|
Settings | Permanent Failure | Enabled PF B | H1 | 0x00 | 0xFF | 0x00 | — |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | RSVD | RSVD | VIMA | VIMR | RSVD | RSVD | RSVD |
RSVD (Bits 7–5): Reserved. Do not use. | ||
VIMA (Bit 4): Voltage Imbalance When Active | ||
1 = | Enabled (default) | |
0 = | Disabled | |
VIMR (Bit 3): Voltage Imbalance At Rest | ||
1 = | Enabled (default) | |
0 = | Disabled | |
RSVD (Bits 2–0): Reserved. Do not use. |