SLUUB41A May   2014  – October 2021 BQ76920 , BQ76930 , BQ76940

 

  1.   Trademarks
  2. 1 Device Features
    1. 1.1  Can I use the part as a standalone protector?
    2. 1.2  Can I use my microcontroller with the AFE?
    3. 1.3  I have a design with the BQ76925 AFE. Can I extend that design to more cells with this AFE?
    4. 1.4  Which cells should I short to reduce the cell count?
    5. 1.5  The VC1 pin has a higher absolute maximum than VC0. Can I short cell 1 and get the benefit of the additional margin to VSS on my lowest cell?
    6. 1.6  Open cell detection is not mentioned in the data sheet. Does the device have this feature?
    7. 1.7  When does the device recover from a fault?
    8. 1.8  How do I clear the status register bits, address 0x00?
    9. 1.9  When the fault bit is cleared in the SYS_STAT register, the FETs do not turn back on. Is this correct?
    10. 1.10 Is an automotive grade version available?
    11. 1.11 For higher cell counts such as 20 cells, is there any recommendation on how to stack the BQ76940 devices?
    12. 1.12 Why is the DEVICE_XREADY bit high on my part and it cannot be cleared?
    13. 1.13 How can I tell if the voltage readings are correct or dormant values?
    14. 1.14 Will the BQ769x0 share the bus with a BQ34z100-G1?
    15. 1.15 What is the ALERT pin timing?
  3. 2 Unused Pins
    1. 2.1 SRP and SRN
    2. 2.2 TS1, TS2, TS3
    3. 2.3 CHG and DSG
    4. 2.4 NC pins
  4. 3 FETs
    1. 3.1  When does the AFE turn on FETs?
    2. 3.2  Can the device drive high-side FETs?
    3. 3.3  Will load detection work with high-side FET configurations?
    4. 3.4  Does load present detection work with the charge FET on?
    5. 3.5  How does the part detect a load?
    6. 3.6  Will load detection work with parallel FET configurations?
    7. 3.7  The charge FET driver uses resistive turn off of the FET. Would this affect the turn off speed of the charge MOSFET, and would this be the way too long?
    8. 3.8  The source capability for both CHG and DSG pin is not in the data sheet. What is the typical output voltage for CHG and DSG pin?
    9. 3.9  Does the AFE turn off the FETs when it loses adequate drive voltage for the FETs?
    10. 3.10 Can I drive multiple FETs in parallel for higher current?
    11. 3.11 Can my circuit be configured with split charge and discharge paths?
  5. 4 ADC
    1. 4.1 Why is the ADC not reading 0x3FFF at 6 V?
    2. 4.2 How do I calculate the battery voltage from the BAT_HI and BAT_LO ADC registers?
    3. 4.3 How do I apply the calibration voltages?
    4. 4.4 Can I calibrate the voltages?
  6. 5 Coulomb Counter (CC)
    1. 5.1 How do I understand the data range of the CC?
    2. 5.2 How does the CC range match to the SC protection levels?
    3. 5.3 How does the CC support the current protection thresholds?
    4. 5.4 How do I measure instantaneous current with the CC?
    5. 5.5 The CC resolution is described in volts (mV, µV). How do I determine current?
    6. 5.6 Why does the CC value read not change when I set the CC_ONESHOT bit?
    7. 5.7 Why does the CC show a different value after shutdown and wake up?
  7. 6 Communications
    1. 6.1  Is the communications interface fully I2C compliant?
    2. 6.2  Does the communications interface support sequential register reads?
    3. 6.3  Why does my voltage (or current) read erratically?
    4. 6.4  Where can I get information on the communications CRC?
    5. 6.5  Can I use the CRC part without CRC?
    6. 6.6  Does the part need pullups on the SDA and SCL lines?
    7. 6.7  Does the BQ769x0 AFE ever drive the SCL line?
    8. 6.8  When does the CC_Ready bit in the SYS_STAT release?
    9. 6.9  What is the communication protocol for the cell groups (internal stacked device)? Is it still I2C?
    10. 6.10 When the PACK– is switched off, will the part be damaged when the communication signals pull to PACK+?
    11. 6.11 Is there a version or can I get the part with a SMBus interface?
    12. 6.12 Is the companion controller interface SMBus and does it use SBS Data format?
    13. 6.13 Why does the AFE not ACK its address?
  8. 7 Temperature Sensing
    1. 7.1 Where are the temperature sensing thresholds?
    2. 7.2 I’m switching the temperature source selection bit TEMP_SEL, but I don’t see the temperature change, why?
    3. 7.3 I only want to use one temperature sensor. Can I leave the others unconnected?
    4. 7.4 Are the NTC temperature sensors required for operation?
    5. 7.5 I want more than three temperature sensors on the BQ76940. Can I multiplex more sensors?
    6. 7.6 Previous gas gauge designs have had a resistor in parallel with the thermistor. Is this needed with the BQ769x0?
    7. 7.7 Do I need a capacitor across the thermistor?
    8. 7.8 How do I understand the die temperature drift specification?
  9. 8 Calibration
    1. 8.1 How do I calibrate current and voltage on the device? Is calibration done on the part at the factory, or do I need to do something at production?
    2. 8.2 Can I set each device to a different voltage setting?
    3. 8.3 Can I set a different threshold for each cell input?
    4. 8.4 Can I make adjustments to calibration for higher accuracy in my system?
    5. 8.5 Other TI protectors have had coarse OV settings. Can I achieve better resolution with the BQ769x0?
    6. 8.6 Can I change the thresholds dynamically during operation, and if so what is the timing on register writes to take effect?
    7. 8.7 Can I block write to the EEPROM?
  10. 9 Cell Balancing
    1. 9.1  How does balancing work?
    2. 9.2  Can I balance all cells at once?
    3. 9.3  Is it safe to balance every other cell?
    4. 9.4  How many cells can I balance at once?
    5. 9.5  Is it okay to balance adjacent cells?
    6. 9.6  The standard schematic uses large value input filter resistors. How can I achieve the maximum internal balance current?
    7. 9.7  Can the BQ769x0 support external balancing?
    8. 9.8  Can I use single-ended capacitor connections for my input filter rather than the differential connection shown in the system diagram?
    9. 9.9  Can the device turn off balance FETs by itself?
    10. 9.10 How much does the temperature rise during balancing?
    11. 9.11 Why does the cell voltage change during balancing?
  11. 10Power
    1. 10.1  Can I short all cell inputs to ground while applying BAT?
    2. 10.2  What is the limit of VC15 (or the top used cell input) with respect to BAT?
    3. 10.3  Can REGSRC operate at a higher voltage than VC5X?
    4. 10.4  Can I connect cells randomly?
    5. 10.5  Why does the application diagram have Rf and Cf and why points A and B?
    6. 10.6  Will the part be damaged if points A and B are floated?
    7. 10.7  Can the Cf have a lower voltage rating than the PACK voltage?
    8. 10.8  The data sheet shows a large variation in power supply current (IDD). Will this cause large offset currents between cell sets?
    9. 10.9  Is there a load mismatch on the cell groups?
    10. 10.10 When I measure supply and offset currents, why do I see peak values much higher than the data sheet maximums?
    11. 10.11 Does connecting fewer than the maximum cells, for example, 13 cells, on a BQ76940 create an imbalance in the cell groups?
    12. 10.12 How can I reset the part?
    13. 10.13 Can the device be reset by a power transient?
    14. 10.14 Will an excessive load (short circuit) on REGOUT reset the part?
    15. 10.15 Why is a FET source follower used for REGSRC?
    16. 10.16 Do I need a large package on the REGSRC FET?
    17. 10.17 Does the external REGSRC FET gain affect the LDO response?
    18. 10.18 What is the efficiency of the LDO?
    19. 10.19 What is the maximum LDO current?
    20. 10.20 Will the part operate properly with transients below VSHUT?
    21. 10.21 Can I use a hold-up circuit on the BAT or REGSRC pin, or both, to extend the operating time under pack short circuit or overcurrent conditions?
    22. 10.22 I will not use the REGOUT voltage from the AFE. Do I still need to supply REGSRC and a capacitor on REGOUT?
  12. 11Power State Switching
    1. 11.1 When entering SHIP mode, will the AFE or controller enter the low power state first?
    2. 11.2 When the pack wakes up, will the AFE or controller wake up first?
    3. 11.3 What happens if my boot switch sticks or the boot signal is left on?
  13. 12EVM
    1. 12.1  Will there be an evaluation module (EVM) for the devices or family?
    2. 12.2  The EVM has a TI controller, can I use my own?
    3. 12.3  My controller is 5 V. Can I use this with the BQ769x0 and EVM?
    4. 12.4  Can I talk to both the SMBus and I2C on the EVM at the same time?
    5. 12.5  Can I configure fewer than the maximum cells on the EVM?
    6. 12.6  I want to configure fewer cells on my EVM. Which cells should I short?
    7. 12.7  What TI interface can I use to communicate with the device?
    8. 12.8  Can I use my existing BQxx EVSW for communication with the EVM?
    9. 12.9  Can I implement external balancing on the EVM?
    10. 12.10 Where can I get the AFE software for the EVM?
    11. 12.11 Is the EVM a finished design?
    12. 12.12 The BQ78350 gauge on the EVM does not respond. How do I get the gauge to work?
  14. 13Revision History

9.5 Is it okay to balance adjacent cells?

The data sheet states that adjacent cells should not be balanced simultaneously. The part does not restrict selection of adjacent cells.

Whether it is safe depends on which cells are balancing and the cell voltages. If 2 adjacent cells are balanced, the VCx pin between the cells does not change significantly in voltage. The differential input voltage of the next cell effectively doubles. If voltages impressed on the device are within the absolute maximum limits (both single-ended and differential), this is okay.

As an example, assume all cells are at 4 V. If cells 4 and 5 are balanced, the VC3 input pulls to VC4, which is approximately the cell 4 voltage or 16 V. This is within the single-ended absolute maximum voltage of 3 × 7.2 = 21.6 V. VC3-VC2 voltage doubles, or is 8 V; this is within the 9-V absolute maximum differential voltage for this input pair. So this balance combination should be okay. However, if cell 1 and cell 2 are balanced, VC0 pulls to the cell 1 value of 4 V. Because this is above the absolute maximum of 3.6 V, this combination of balancing could damage the device and should not be selected.

As another example, if the cell voltages are 3.6 V, the absolute maximum on VC0 from the above example would not be violated, and cells 1 and 2 could be balanced at the same time. However, if cells 4 and 5 were also simultaneously selected for balancing, VC2 would be approximately the cell 1 voltage of 3.6 V and VC3 would be approximately the cell 4 voltage of 14.4 V. VC3-VC2 would be 10.8 V and would exceed the absolute maximum of 9 V.

When external balancing is used, the control voltage for the external FETs is developed across the input resistor. With adjacent cells selected for balancing, one of the FETs may not receive an adequate control voltage and its balancing will be ineffective.

Adjacent cells in adjacent groups may be balanced simultaneously, for example cells 5 and 6 with a BQ76930. Because the cells are in different groups, they have separate input resistors for each group and the balancing can operate independently, even with external balancing. Be cautious of common path resistances between groups. See Section 4 of the BQ769x0 Family Top 10 Design Considerations document for more information.

Because of the complexity of determining when adjacent cell balancing may be safe, the user should follow the data sheet recommendation.